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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ | 5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ |
6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ | 6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ |
7 | 7 |
8 #ifndef RUNTIME_VM_ASSEMBLER_H_ | 8 #ifndef RUNTIME_VM_ASSEMBLER_H_ |
9 #error Do not include assembler_arm64.h directly; use assembler.h instead. | 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. |
10 #endif | 10 #endif |
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735 (a.type() == Address::PairPreIndex)); | 735 (a.type() == Address::PairPreIndex)); |
736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); | 736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); |
737 } | 737 } |
738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { | 738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { |
739 ASSERT((a.type() == Address::PairOffset) || | 739 ASSERT((a.type() == Address::PairOffset) || |
740 (a.type() == Address::PairPostIndex) || | 740 (a.type() == Address::PairPostIndex) || |
741 (a.type() == Address::PairPreIndex)); | 741 (a.type() == Address::PairPreIndex)); |
742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); | 742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); |
743 } | 743 } |
744 | 744 |
745 void ldxr(Register rt, Register rn) { | 745 void ldxr(Register rt, Register rn, OperandSize size = kDoubleWord) { |
746 // rt = value | 746 // rt = value |
747 // rn = address | 747 // rn = address |
748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord); | 748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, size); |
749 } | 749 } |
750 void stxr(Register rs, Register rt, Register rn) { | 750 void stxr(Register rs, |
| 751 Register rt, |
| 752 Register rn, |
| 753 OperandSize size = kDoubleWord) { |
751 // rs = status (1 = failure, 0 = success) | 754 // rs = status (1 = failure, 0 = success) |
752 // rt = value | 755 // rt = value |
753 // rn = address | 756 // rn = address |
754 EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord); | 757 EmitLoadStoreExclusive(STXR, rs, rn, rt, size); |
755 } | 758 } |
756 void clrex() { | 759 void clrex() { |
757 const int32_t encoding = static_cast<int32_t>(CLREX); | 760 const int32_t encoding = static_cast<int32_t>(CLREX); |
758 Emit(encoding); | 761 Emit(encoding); |
759 } | 762 } |
760 | 763 |
761 // Conditional select. | 764 // Conditional select. |
762 void csel(Register rd, Register rn, Register rm, Condition cond) { | 765 void csel(Register rd, Register rn, Register rm, Condition cond) { |
763 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); | 766 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); |
764 } | 767 } |
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1694 (static_cast<int32_t>(hw_idx) << kHWShift) | | 1697 (static_cast<int32_t>(hw_idx) << kHWShift) | |
1695 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); | 1698 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); |
1696 Emit(encoding); | 1699 Emit(encoding); |
1697 } | 1700 } |
1698 | 1701 |
1699 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, | 1702 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, |
1700 Register rs, | 1703 Register rs, |
1701 Register rn, | 1704 Register rn, |
1702 Register rt, | 1705 Register rt, |
1703 OperandSize sz = kDoubleWord) { | 1706 OperandSize sz = kDoubleWord) { |
1704 ASSERT(sz == kDoubleWord); | 1707 ASSERT(sz == kDoubleWord || sz == kWord); |
1705 const int32_t size = B31 | B30; | 1708 const int32_t size = B31 | (sz == kDoubleWord ? B30 : 0); |
1706 | 1709 |
1707 ASSERT((rs != kNoRegister) && (rs != ZR)); | 1710 ASSERT((rs != kNoRegister) && (rs != ZR)); |
1708 ASSERT((rn != kNoRegister) && (rn != ZR)); | 1711 ASSERT((rn != kNoRegister) && (rn != ZR)); |
1709 ASSERT((rt != kNoRegister) && (rt != ZR)); | 1712 ASSERT((rt != kNoRegister) && (rt != ZR)); |
1710 | 1713 |
1711 const int32_t encoding = | 1714 const int32_t encoding = |
1712 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | | 1715 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | |
1713 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | | 1716 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | |
1714 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); | 1717 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); |
1715 | 1718 |
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1934 Register value, | 1937 Register value, |
1935 Label* no_update); | 1938 Label* no_update); |
1936 | 1939 |
1937 DISALLOW_ALLOCATION(); | 1940 DISALLOW_ALLOCATION(); |
1938 DISALLOW_COPY_AND_ASSIGN(Assembler); | 1941 DISALLOW_COPY_AND_ASSIGN(Assembler); |
1939 }; | 1942 }; |
1940 | 1943 |
1941 } // namespace dart | 1944 } // namespace dart |
1942 | 1945 |
1943 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ | 1946 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ |
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