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Side by Side Diff: runtime/vm/simulator_arm64.cc

Issue 2953753002: Revert "Inline instance object hash code into object header on 64 bit." (Closed)
Patch Set: Created 3 years, 6 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include <setjmp.h> // NOLINT 5 #include <setjmp.h> // NOLINT
6 #include <stdlib.h> 6 #include <stdlib.h>
7 7
8 #include "vm/globals.h" 8 #include "vm/globals.h"
9 #if defined(TARGET_ARCH_ARM64) 9 #if defined(TARGET_ARCH_ARM64)
10 10
(...skipping 1207 matching lines...) Expand 10 before | Expand all | Expand 10 after
1218 } 1218 }
1219 1219
1220 1220
1221 intptr_t Simulator::ReadExclusiveX(uword addr, Instr* instr) { 1221 intptr_t Simulator::ReadExclusiveX(uword addr, Instr* instr) {
1222 MutexLocker ml(exclusive_access_lock_); 1222 MutexLocker ml(exclusive_access_lock_);
1223 SetExclusiveAccess(addr); 1223 SetExclusiveAccess(addr);
1224 return ReadX(addr, instr); 1224 return ReadX(addr, instr);
1225 } 1225 }
1226 1226
1227 1227
1228 intptr_t Simulator::ReadExclusiveW(uword addr, Instr* instr) {
1229 MutexLocker ml(exclusive_access_lock_);
1230 SetExclusiveAccess(addr);
1231 return ReadWU(addr, instr);
1232 }
1233
1234
1235 intptr_t Simulator::WriteExclusiveX(uword addr, intptr_t value, Instr* instr) { 1228 intptr_t Simulator::WriteExclusiveX(uword addr, intptr_t value, Instr* instr) {
1236 MutexLocker ml(exclusive_access_lock_); 1229 MutexLocker ml(exclusive_access_lock_);
1237 bool write_allowed = HasExclusiveAccessAndOpen(addr); 1230 bool write_allowed = HasExclusiveAccessAndOpen(addr);
1238 if (write_allowed) { 1231 if (write_allowed) {
1239 WriteX(addr, value, instr); 1232 WriteX(addr, value, instr);
1240 return 0; // Success. 1233 return 0; // Success.
1241 } 1234 }
1242 return 1; // Failure. 1235 return 1; // Failure.
1243 } 1236 }
1244 1237
1245 1238
1246 intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
1247 MutexLocker ml(exclusive_access_lock_);
1248 bool write_allowed = HasExclusiveAccessAndOpen(addr);
1249 if (write_allowed) {
1250 WriteW(addr, value, instr);
1251 return 0; // Success.
1252 }
1253 return 1; // Failure.
1254 }
1255
1256
1257 uword Simulator::CompareExchange(uword* address, 1239 uword Simulator::CompareExchange(uword* address,
1258 uword compare_value, 1240 uword compare_value,
1259 uword new_value) { 1241 uword new_value) {
1260 MutexLocker ml(exclusive_access_lock_); 1242 MutexLocker ml(exclusive_access_lock_);
1261 // We do not get a reservation as it would be guaranteed to be found when 1243 // We do not get a reservation as it would be guaranteed to be found when
1262 // writing below. No other thread is able to make a reservation while we 1244 // writing below. No other thread is able to make a reservation while we
1263 // hold the lock. 1245 // hold the lock.
1264 uword value = *address; 1246 uword value = *address;
1265 if (value == compare_value) { 1247 if (value == compare_value) {
1266 *address = new_value; 1248 *address = new_value;
(...skipping 943 matching lines...) Expand 10 before | Expand all | Expand 10 after
2210 set_wregister(rt, static_cast<int32_t>(val), R31IsZR); 2192 set_wregister(rt, static_cast<int32_t>(val), R31IsZR);
2211 } 2193 }
2212 } 2194 }
2213 2195
2214 2196
2215 void Simulator::DecodeLoadStoreExclusive(Instr* instr) { 2197 void Simulator::DecodeLoadStoreExclusive(Instr* instr) {
2216 if ((instr->Bit(23) != 0) || (instr->Bit(21) != 0) || (instr->Bit(15) != 0)) { 2198 if ((instr->Bit(23) != 0) || (instr->Bit(21) != 0) || (instr->Bit(15) != 0)) {
2217 UNIMPLEMENTED(); 2199 UNIMPLEMENTED();
2218 } 2200 }
2219 const int32_t size = instr->Bits(30, 2); 2201 const int32_t size = instr->Bits(30, 2);
2220 if (size != 3 && size != 2) { 2202 if (size != 3) {
2221 UNIMPLEMENTED(); 2203 UNIMPLEMENTED();
2222 } 2204 }
2205
2223 const Register rs = instr->RsField(); 2206 const Register rs = instr->RsField();
2224 const Register rn = instr->RnField(); 2207 const Register rn = instr->RnField();
2225 const Register rt = instr->RtField(); 2208 const Register rt = instr->RtField();
2226 const bool is_load = instr->Bit(22) == 1; 2209 const bool is_load = instr->Bit(22) == 1;
2227 if (is_load) { 2210 if (is_load) {
2228 // Format(instr, "ldxr 'rt, 'rn"); 2211 // Format(instr, "ldxr 'rt, 'rn");
2229 if (size == 3) { 2212 const int64_t addr = get_register(rn, R31IsSP);
2230 const int64_t addr = get_register(rn, R31IsSP); 2213 intptr_t value = ReadExclusiveX(addr, instr);
2231 intptr_t value = ReadExclusiveX(addr, instr); 2214 set_register(instr, rt, value, R31IsSP);
2232 set_register(instr, rt, value, R31IsSP);
2233 } else {
2234 const int64_t addr = get_register(rn, R31IsSP);
2235 intptr_t value = ReadExclusiveW(addr, instr);
2236 set_register(instr, rt, value, R31IsSP);
2237 }
2238 } else { 2215 } else {
2239 // Format(instr, "stxr 'rs, 'rt, 'rn"); 2216 // Format(instr, "stxr 'rs, 'rt, 'rn");
2240 if (size == 3) { 2217 uword value = get_register(rt, R31IsSP);
2241 uword value = get_register(rt, R31IsSP); 2218 uword addr = get_register(rn, R31IsSP);
2242 uword addr = get_register(rn, R31IsSP); 2219 intptr_t status = WriteExclusiveX(addr, value, instr);
2243 intptr_t status = WriteExclusiveX(addr, value, instr); 2220 set_register(instr, rs, status, R31IsSP);
2244 set_register(instr, rs, status, R31IsSP);
2245 } else {
2246 uint32_t value = get_register(rt, R31IsSP);
2247 uword addr = get_register(rn, R31IsSP);
2248 intptr_t status = WriteExclusiveW(addr, value, instr);
2249 set_register(instr, rs, status, R31IsSP);
2250 }
2251 } 2221 }
2252 } 2222 }
2253 2223
2254 2224
2255 void Simulator::DecodeLoadStore(Instr* instr) { 2225 void Simulator::DecodeLoadStore(Instr* instr) {
2256 if (instr->IsLoadStoreRegOp()) { 2226 if (instr->IsLoadStoreRegOp()) {
2257 DecodeLoadStoreReg(instr); 2227 DecodeLoadStoreReg(instr);
2258 } else if (instr->IsLoadStoreRegPairOp()) { 2228 } else if (instr->IsLoadStoreRegPairOp()) {
2259 DecodeLoadStoreRegPair(instr); 2229 DecodeLoadStoreRegPair(instr);
2260 } else if (instr->IsLoadRegLiteralOp()) { 2230 } else if (instr->IsLoadRegLiteralOp()) {
(...skipping 1436 matching lines...) Expand 10 before | Expand all | Expand 10 after
3697 set_register(NULL, CODE_REG, code); 3667 set_register(NULL, CODE_REG, code);
3698 set_register(NULL, PP, pp); 3668 set_register(NULL, PP, pp);
3699 buf->Longjmp(); 3669 buf->Longjmp();
3700 } 3670 }
3701 3671
3702 } // namespace dart 3672 } // namespace dart
3703 3673
3704 #endif // !defined(USING_SIMULATOR) 3674 #endif // !defined(USING_SIMULATOR)
3705 3675
3706 #endif // defined TARGET_ARCH_ARM64 3676 #endif // defined TARGET_ARCH_ARM64
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