Adds more SIMD instructions to arm64.

runtime/vm/flow_graph_compiler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "vm/ast_printer.h"
@@ skipping 1422 matching lines @@
 void FlowGraphCompiler::SaveLiveRegisters(LocationSummary* locs) {
   // TODO(vegorov): consider saving only caller save (volatile) registers.
   const intptr_t fpu_regs_count = locs->live_registers()->FpuRegisterCount();
   if (fpu_regs_count > 0) {
     // Store fpu registers with the lowest register number at the lowest
     // address.
     for (intptr_t reg_idx = kNumberOfVRegisters - 1;
                   reg_idx >= 0; --reg_idx) {
       VRegister fpu_reg = static_cast<VRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        // TODO(zra): Save the whole V register.
-        __ PushDouble(fpu_reg);
+        __ PushQuad(fpu_reg);
       }
     }
   }
 
   // Store general purpose registers with the highest register number at the
   // lowest address.
   for (intptr_t reg_idx = 0; reg_idx < kNumberOfCpuRegisters; ++reg_idx) {
     Register reg = static_cast<Register>(reg_idx);
     if (locs->live_registers()->ContainsRegister(reg)) {
       __ Push(reg);
@@ skipping 11 matching lines @@
       __ Pop(reg);
     }
   }
 
   const intptr_t fpu_regs_count = locs->live_registers()->FpuRegisterCount();
   if (fpu_regs_count > 0) {
     // Fpu registers have the lowest register number at the lowest address.
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfVRegisters; ++reg_idx) {
       VRegister fpu_reg = static_cast<VRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        // TODO(zra): Restore the whole V register.
-        __ PopDouble(fpu_reg);
+        __ PopQuad(fpu_reg);
       }
     }
   }
 }
 
 
 void FlowGraphCompiler::EmitTestAndCall(const ICData& ic_data,
                                         Register class_id_reg,
                                         intptr_t argument_count,
                                         const Array& argument_names,
@@ skipping 100 matching lines @@
       __ LoadFromOffset(destination.reg(), FP, source_offset, PP);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadFromOffset(TMP, FP, source_offset, PP);
       __ StoreToOffset(TMP, FP, dest_offset, PP);
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
-      __ fmovdd(destination.fpu_reg(), source.fpu_reg());
+      __ vmov(destination.fpu_reg(), source.fpu_reg());
     } else {
       if (destination.IsDoubleStackSlot()) {
         const intptr_t dest_offset = destination.ToStackSlotOffset();
         VRegister src = source.fpu_reg();
         __ StoreDToOffset(src, FP, dest_offset, PP);
       } else {
         ASSERT(destination.IsQuadStackSlot());
-        UNIMPLEMENTED();
+        const intptr_t dest_offset = destination.ToStackSlotOffset();
+        __ StoreQToOffset(source.fpu_reg(), FP, dest_offset, PP);
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
       const intptr_t dest_offset = source.ToStackSlotOffset();
       const VRegister dst = destination.fpu_reg();
       __ LoadDFromOffset(dst, FP, dest_offset, PP);
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadDFromOffset(VTMP, FP, source_offset, PP);
       __ StoreDToOffset(VTMP, FP, dest_offset, PP);
     }
   } else if (source.IsQuadStackSlot()) {
-    UNIMPLEMENTED();
+    if (destination.IsFpuRegister()) {
+      const intptr_t dest_offset = source.ToStackSlotOffset();
+      __ LoadQFromOffset(destination.fpu_reg(), FP, dest_offset, PP);
+    } else {
+      ASSERT(destination.IsQuadStackSlot());
+      const intptr_t source_offset = source.ToStackSlotOffset();
+      const intptr_t dest_offset = destination.ToStackSlotOffset();
+      __ LoadQFromOffset(VTMP, FP, source_offset, PP);
+      __ StoreQToOffset(VTMP, FP, dest_offset, PP);
+    }
   } else {
     ASSERT(source.IsConstant());
     const Object& constant = source.constant();
     if (destination.IsRegister()) {
       __ LoadObject(destination.reg(), constant, PP);
     } else if (destination.IsFpuRegister()) {
       const VRegister dst = destination.fpu_reg();
       __ LoadObject(TMP, constant, PP);
       __ LoadDFieldFromOffset(dst, TMP, Double::value_offset(), PP);
     } else if (destination.IsDoubleStackSlot()) {
@@ skipping 144 matching lines @@
 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
   UNIMPLEMENTED();
 }
 
 
 #undef __
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64