Adds more SIMD instructions to arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 424 matching lines @@
   void subs(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, true, true, rd, rn, o);
   }
 
   // PC relative immediate add. imm is in bytes.
   void adr(Register rd, int64_t imm) {
     EmitPCRelOp(ADR, rd, imm);
   }
 
   // Logical immediate operations.
-  // TODO(zra): Add macros that check IsImmLogical, and fall back on a longer
-  // sequence on failure.
   void andi(Register rd, Register rn, uint64_t imm) {
     Operand imm_op;
     const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
     ASSERT(immok);
     EmitLogicalImmOp(ANDI, rd, rn, imm_op, kDoubleWord);
   }
   void orri(Register rd, Register rn, uint64_t imm) {
     Operand imm_op;
     const bool immok = Operand::IsImmLogical(imm, kXRegSizeInBits, &imm_op);
     ASSERT(immok);
@@ skipping 270 matching lines @@
     EmitFPTwoSourceOp(FDIVD, vd, vn, vm);
   }
   void faddd(VRegister vd, VRegister vn, VRegister vm) {
     EmitFPTwoSourceOp(FADDD, vd, vn, vm);
   }
   void fsubd(VRegister vd, VRegister vn, VRegister vm) {
     EmitFPTwoSourceOp(FSUBD, vd, vn, vm);
   }
 
   // SIMD operations.
+  void vand(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VAND, vd, vn, vm);
+  }
+  void vorr(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VORR, vd, vn, vm);
+  }
+  void veor(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VEOR, vd, vn, vm);
+  }
+  void vaddw(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VADDW, vd, vn, vm);
+  }
+  void vaddx(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VADDX, vd, vn, vm);
+  }
+  void vsubw(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VSUBW, vd, vn, vm);
+  }
+  void vsubx(VRegister vd, VRegister vn, VRegister vm) {
+    EmitSIMDThreeSameOp(VSUBX, vd, vn, vm);
+  }
   void vadds(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VADDS, vd, vn, vm);
   }
   void vaddd(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VADDD, vd, vn, vm);
   }
   void vsubs(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VSUBS, vd, vn, vm);
   }
   void vsubd(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VSUBD, vd, vn, vm);
   }
   void vmuls(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VMULS, vd, vn, vm);
   }
   void vmuld(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VMULD, vd, vn, vm);
   }
   void vdivs(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VDIVS, vd, vn, vm);
   }
   void vdivd(VRegister vd, VRegister vn, VRegister vm) {
     EmitSIMDThreeSameOp(VDIVD, vd, vn, vm);
   }
+  void vnot(VRegister vd, VRegister vn) {
+    EmitSIMDTwoRegOp(VNOT, vd, vn);
+  }
+  void vabss(VRegister vd, VRegister vn) {
+    EmitSIMDTwoRegOp(VABSS, vd, vn);
+  }
+  void vabsd(VRegister vd, VRegister vn) {
+    EmitSIMDTwoRegOp(VABSD, vd, vn);
+  }
+  void vnegs(VRegister vd, VRegister vn) {
+    EmitSIMDTwoRegOp(VNEGS, vd, vn);
+  }
+  void vnegd(VRegister vd, VRegister vn) {
+    EmitSIMDTwoRegOp(VNEGD, vd, vn);
+  }
+  void vdupw(VRegister vd, Register rn) {
+    const VRegister vn = static_cast<VRegister>(rn);
+    EmitSIMDCopyOp(VDUPI, vd, vn, kWord, 0, 0);
+  }
+  void vdupx(VRegister vd, Register rn) {
+    const VRegister vn = static_cast<VRegister>(rn);
+    EmitSIMDCopyOp(VDUPI, vd, vn, kDoubleWord, 0, 0);
+  }
   void vdups(VRegister vd, VRegister vn, int32_t idx) {
     EmitSIMDCopyOp(VDUP, vd, vn, kSWord, 0, idx);
   }
   void vdupd(VRegister vd, VRegister vn, int32_t idx) {
     EmitSIMDCopyOp(VDUP, vd, vn, kDWord, 0, idx);
   }
+  void vinsw(VRegister vd, int32_t didx, Register rn) {
+    const VRegister vn = static_cast<VRegister>(rn);
+    EmitSIMDCopyOp(VINSI, vd, vn, kWord, 0, didx);
+  }
+  void vinsx(VRegister vd, int32_t didx, Register rn) {
+    const VRegister vn = static_cast<VRegister>(rn);
+    EmitSIMDCopyOp(VINSI, vd, vn, kDoubleWord, 0, didx);
+  }
   void vinss(VRegister vd, int32_t didx, VRegister vn, int32_t sidx) {
     EmitSIMDCopyOp(VINS, vd, vn, kSWord, sidx, didx);
   }
   void vinsd(VRegister vd, int32_t didx, VRegister vn, int32_t sidx) {
     EmitSIMDCopyOp(VINS, vd, vn, kDWord, sidx, didx);
   }
+  void vmovrs(Register rd, VRegister vn, int32_t sidx) {
+    const VRegister vd = static_cast<VRegister>(rd);
+    EmitSIMDCopyOp(VMOVW, vd, vn, kWord, 0, sidx);
+  }
+  void vmovrd(Register rd, VRegister vn, int32_t sidx) {
+    const VRegister vd = static_cast<VRegister>(rd);
+    EmitSIMDCopyOp(VMOVX, vd, vn, kDoubleWord, 0, sidx);
+  }
 
   // Aliases.
   void mov(Register rd, Register rn) {
     if ((rd == SP) || (rn == SP)) {
       add(rd, rn, Operand(0));
     } else {
       orr(rd, ZR, Operand(rn));
     }
   }
+  void vmov(VRegister vd, VRegister vn) {
+    vorr(vd, vn, vn);
+  }
   void mvn(Register rd, Register rm) {
     orn(rd, ZR, Operand(rm));
   }
   void neg(Register rd, Register rm) {
     sub(rd, ZR, Operand(rm));
   }
   void negs(Register rd, Register rm) {
     subs(rd, ZR, Operand(rm));
   }
   void mul(Register rd, Register rn, Register rm) {
     madd(rd, rn, rm, ZR);
   }
   void Push(Register reg) {
     ASSERT(reg != PP);  // Only push PP with TagAndPushPP().
     str(reg, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void Pop(Register reg) {
     ASSERT(reg != PP);  // Only pop PP with PopAndUntagPP().
     ldr(reg, Address(SP, 1 * kWordSize, Address::PostIndex));
   }
+  void PushFloat(VRegister reg) {
+    fstrs(reg, Address(SP, -1 * kFloatSize, Address::PreIndex));
+  }
   void PushDouble(VRegister reg) {
-    fstrd(reg, Address(SP, -1 * kWordSize, Address::PreIndex));
+    fstrd(reg, Address(SP, -1 * kDoubleSize, Address::PreIndex));
+  }
+  void PushQuad(VRegister reg) {
+    fstrq(reg, Address(SP, -1 * kQuadSize, Address::PreIndex));
+  }
+  void PopFloat(VRegister reg) {
+    fldrs(reg, Address(SP, 1 * kFloatSize, Address::PostIndex));
   }
   void PopDouble(VRegister reg) {
-    fldrd(reg, Address(SP, 1 * kWordSize, Address::PostIndex));
+    fldrd(reg, Address(SP, 1 * kDoubleSize, Address::PostIndex));
+  }
+  void PopQuad(VRegister reg) {
+    fldrq(reg, Address(SP, 1 * kQuadSize, Address::PostIndex));
   }
   void TagAndPushPP() {
     // Add the heap object tag back to PP before putting it on the stack.
     add(TMP, PP, Operand(kHeapObjectTag));
     str(TMP, Address(SP, -1 * kWordSize, Address::PreIndex));
   }
   void PopAndUntagPP() {
     ldr(PP, Address(SP, 1 * kWordSize, Address::PostIndex));
     sub(PP, PP, Operand(kHeapObjectTag));
   }
@@ skipping 640 matching lines @@
     const int32_t imm4 = (idx4 << shift) & 0xf;
     const int32_t encoding =
         op |
         (imm5 << kImm5Shift) |
         (imm4 << kImm4Shift) |
         (static_cast<int32_t>(vd) << kVdShift) |
         (static_cast<int32_t>(vn) << kVnShift);
     Emit(encoding);
   }
 
+  void EmitSIMDTwoRegOp(SIMDTwoRegOp op, VRegister vd, VRegister vn) {
+    const int32_t encoding =
+        op |
+        (static_cast<int32_t>(vd) << kVdShift) |
+        (static_cast<int32_t>(vn) << kVnShift);
+    Emit(encoding);
+  }
+
   void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
 
   // Shorter filtering sequence that assumes that value is not a smi.
   void StoreIntoObjectFilterNoSmi(Register object,
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_