Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(362)

Side by Side Diff: runtime/vm/intermediate_language_arm.cc

Issue 295243005: Adds more SIMD instructions to arm64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
OLDNEW
1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/intermediate_language.h" 8 #include "vm/intermediate_language.h"
9 9
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
(...skipping 3908 matching lines...) Expand 10 before | Expand all | Expand 10 after
3919 const QRegister result = locs()->out(0).fpu_reg(); 3919 const QRegister result = locs()->out(0).fpu_reg();
3920 const DRegister dresult0 = EvenDRegisterOf(result); 3920 const DRegister dresult0 = EvenDRegisterOf(result);
3921 const DRegister dresult1 = OddDRegisterOf(result); 3921 const DRegister dresult1 = OddDRegisterOf(result);
3922 const SRegister sresult0 = EvenSRegisterOf(dresult0); 3922 const SRegister sresult0 = EvenSRegisterOf(dresult0);
3923 const SRegister sresult1 = OddSRegisterOf(dresult0); 3923 const SRegister sresult1 = OddSRegisterOf(dresult0);
3924 const SRegister sresult2 = EvenSRegisterOf(dresult1); 3924 const SRegister sresult2 = EvenSRegisterOf(dresult1);
3925 const SRegister sresult3 = OddSRegisterOf(dresult1); 3925 const SRegister sresult3 = OddSRegisterOf(dresult1);
3926 3926
3927 const DRegister dvalue0 = EvenDRegisterOf(value); 3927 const DRegister dvalue0 = EvenDRegisterOf(value);
3928 const DRegister dvalue1 = OddDRegisterOf(value); 3928 const DRegister dvalue1 = OddDRegisterOf(value);
3929 const SRegister svalue0 = EvenSRegisterOf(dvalue0);
3930 const SRegister svalue1 = OddSRegisterOf(dvalue0);
3931 const SRegister svalue2 = EvenSRegisterOf(dvalue1);
3932 const SRegister svalue3 = OddSRegisterOf(dvalue1);
3929 3933
3930 const DRegister dtemp0 = DTMP; 3934 const DRegister dtemp0 = DTMP;
3931 const DRegister dtemp1 = OddDRegisterOf(QTMP); 3935 const DRegister dtemp1 = OddDRegisterOf(QTMP);
3932 3936
3933 // For some cases the vdup instruction requires fewer 3937 // For some cases the vdup instruction requires fewer
3934 // instructions. For arbitrary shuffles, use vtbl. 3938 // instructions. For arbitrary shuffles, use vtbl.
3935 3939
3936 switch (op_kind()) { 3940 switch (op_kind()) {
3937 case MethodRecognizer::kFloat32x4ShuffleX: 3941 case MethodRecognizer::kFloat32x4ShuffleX:
3938 __ vdup(kWord, result, dvalue0, 0); 3942 __ vcvtds(dresult0, svalue0);
3939 __ vcvtds(dresult0, sresult0);
3940 break; 3943 break;
3941 case MethodRecognizer::kFloat32x4ShuffleY: 3944 case MethodRecognizer::kFloat32x4ShuffleY:
3942 __ vdup(kWord, result, dvalue0, 1); 3945 __ vcvtds(dresult0, svalue1);
3943 __ vcvtds(dresult0, sresult0);
3944 break; 3946 break;
3945 case MethodRecognizer::kFloat32x4ShuffleZ: 3947 case MethodRecognizer::kFloat32x4ShuffleZ:
3946 __ vdup(kWord, result, dvalue1, 0); 3948 __ vcvtds(dresult0, svalue2);
3947 __ vcvtds(dresult0, sresult0);
3948 break; 3949 break;
3949 case MethodRecognizer::kFloat32x4ShuffleW: 3950 case MethodRecognizer::kFloat32x4ShuffleW:
3950 __ vdup(kWord, result, dvalue1, 1); 3951 __ vcvtds(dresult0, svalue3);
3951 __ vcvtds(dresult0, sresult0);
3952 break; 3952 break;
3953 case MethodRecognizer::kInt32x4Shuffle: 3953 case MethodRecognizer::kInt32x4Shuffle:
3954 case MethodRecognizer::kFloat32x4Shuffle: 3954 case MethodRecognizer::kFloat32x4Shuffle:
3955 if (mask_ == 0x00) { 3955 if (mask_ == 0x00) {
3956 __ vdup(kWord, result, dvalue0, 0); 3956 __ vdup(kWord, result, dvalue0, 0);
3957 } else if (mask_ == 0x55) { 3957 } else if (mask_ == 0x55) {
3958 __ vdup(kWord, result, dvalue0, 1); 3958 __ vdup(kWord, result, dvalue0, 1);
3959 } else if (mask_ == 0xAA) { 3959 } else if (mask_ == 0xAA) {
3960 __ vdup(kWord, result, dvalue1, 0); 3960 __ vdup(kWord, result, dvalue1, 0);
3961 } else if (mask_ == 0xFF) { 3961 } else if (mask_ == 0xFF) {
(...skipping 976 matching lines...) Expand 10 before | Expand all | Expand 10 after
4938 summary->set_out(0, Location::RequiresFpuRegister()); 4938 summary->set_out(0, Location::RequiresFpuRegister());
4939 return summary; 4939 return summary;
4940 } 4940 }
4941 4941
4942 4942
4943 void BinaryInt32x4OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) { 4943 void BinaryInt32x4OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
4944 const QRegister left = locs()->in(0).fpu_reg(); 4944 const QRegister left = locs()->in(0).fpu_reg();
4945 const QRegister right = locs()->in(1).fpu_reg(); 4945 const QRegister right = locs()->in(1).fpu_reg();
4946 const QRegister result = locs()->out(0).fpu_reg(); 4946 const QRegister result = locs()->out(0).fpu_reg();
4947 switch (op_kind()) { 4947 switch (op_kind()) {
4948 case Token::kBIT_AND: { 4948 case Token::kBIT_AND: __ vandq(result, left, right); break;
4949 __ vandq(result, left, right); 4949 case Token::kBIT_OR: __ vorrq(result, left, right); break;
4950 break; 4950 case Token::kBIT_XOR: __ veorq(result, left, right); break;
4951 } 4951 case Token::kADD: __ vaddqi(kWord, result, left, right); break;
4952 case Token::kBIT_OR: { 4952 case Token::kSUB: __ vsubqi(kWord, result, left, right); break;
4953 __ vorrq(result, left, right);
4954 break;
4955 }
4956 case Token::kBIT_XOR: {
4957 __ veorq(result, left, right);
4958 break;
4959 }
4960 case Token::kADD:
4961 __ vaddqi(kWord, result, left, right);
4962 break;
4963 case Token::kSUB:
4964 __ vsubqi(kWord, result, left, right);
4965 break;
4966 default: UNREACHABLE(); 4953 default: UNREACHABLE();
4967 } 4954 }
4968 } 4955 }
4969 4956
4970 4957
4971 LocationSummary* MathUnaryInstr::MakeLocationSummary(Isolate* isolate, 4958 LocationSummary* MathUnaryInstr::MakeLocationSummary(Isolate* isolate,
4972 bool opt) const { 4959 bool opt) const {
4973 if ((kind() == MathUnaryInstr::kSin) || (kind() == MathUnaryInstr::kCos)) { 4960 if ((kind() == MathUnaryInstr::kSin) || (kind() == MathUnaryInstr::kCos)) {
4974 const intptr_t kNumInputs = 1; 4961 const intptr_t kNumInputs = 1;
4975 const intptr_t kNumTemps = 0; 4962 const intptr_t kNumTemps = 0;
(...skipping 1462 matching lines...) Expand 10 before | Expand all | Expand 10 after
6438 compiler->GenerateCall(token_pos(), 6425 compiler->GenerateCall(token_pos(),
6439 &label, 6426 &label,
6440 PcDescriptors::kOther, 6427 PcDescriptors::kOther,
6441 locs()); 6428 locs());
6442 __ Drop(ArgumentCount()); // Discard arguments. 6429 __ Drop(ArgumentCount()); // Discard arguments.
6443 } 6430 }
6444 6431
6445 } // namespace dart 6432 } // namespace dart
6446 6433
6447 #endif // defined TARGET_ARCH_ARM 6434 #endif // defined TARGET_ARCH_ARM
OLDNEW

Powered by Google App Engine
This is Rietveld 408576698