[arm, arm64] Implemented unaligned scalar float access.

runtime/vm/simulator_arm64.cc

Index: runtime/vm/simulator_arm64.cc
diff --git a/runtime/vm/simulator_arm64.cc b/runtime/vm/simulator_arm64.cc
index 455bac6e80228a81c3d86dbb0bf4d64dce8b7cd7..6125bae52ac4fba69e5680780976a6192c5cf3f1 100644
--- a/runtime/vm/simulator_arm64.cc
+++ b/runtime/vm/simulator_arm64.cc
@@ -3251,33 +3251,52 @@ void Simulator::DecodeFPIntCvt(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
 
-  if ((instr->Bit(29) != 0) || (instr->Bits(22, 2) != 1) ||
-      ((instr->SFField() == 0) && (instr->Bits(16, 5) != 2))) {
+  if (instr->Bit(29) != 0) {
     UnimplementedInstruction(instr);
     return;
   }
-  if (instr->Bits(16, 5) == 2) {
-    // Format(instr, "scvtfd'sf 'vd, 'rn");
-    const int64_t rn_val64 = get_register(rn, instr->RnMode());
-    const int32_t rn_val32 = get_wregister(rn, instr->RnMode());
-    const double vn_dbl = (instr->SFField() == 1)
-                              ? static_cast<double>(rn_val64)
-                              : static_cast<double>(rn_val32);
-    set_vregisterd(vd, 0, bit_cast<int64_t, double>(vn_dbl));
-    set_vregisterd(vd, 1, 0);
-  } else if (instr->Bits(16, 5) == 6) {
-    // Format(instr, "fmovrd'sf 'rd, 'vn");
-    const int64_t vn_val = get_vregisterd(vn, 0);
-    set_register(instr, rd, vn_val, R31IsZR);
-  } else if (instr->Bits(16, 5) == 7) {
-    // Format(instr, "fmovdr'sf 'vd, 'rn");
-    const int64_t rn_val = get_register(rn, R31IsZR);
-    set_vregisterd(vd, 0, rn_val);
-    set_vregisterd(vd, 1, 0);
-  } else if (instr->Bits(16, 5) == 24) {
-    // Format(instr, "fcvtzds'sf 'rd, 'vn");
-    const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
-    set_register(instr, rd, static_cast<int64_t>(vn_val), instr->RdMode());
+
+  if ((instr->SFField() == 0) && (instr->Bits(22, 2) == 0)) {
+    if (instr->Bits(16, 5) == 6) {
+      // Format(instr, "fmovrs'sf 'rd, 'vn");
+      const int32_t vn_val = get_vregisters(vn, 0);
+      set_wregister(rd, vn_val, R31IsZR);
+    } else if (instr->Bits(16, 5) == 7) {
+      // Format(instr, "fmovsr'sf 'vd, 'rn");
+      const int32_t rn_val = get_wregister(rn, R31IsZR);
+      set_vregisters(vd, 0, rn_val);
+      set_vregisters(vd, 1, 0);
+      set_vregisters(vd, 2, 0);
+      set_vregisters(vd, 3, 0);
+    } else {
+      UnimplementedInstruction(instr);
+    }
+  } else if (instr->Bits(22, 2) == 1) {
+    if (instr->Bits(16, 5) == 2) {
+      // Format(instr, "scvtfd'sf 'vd, 'rn");
+      const int64_t rn_val64 = get_register(rn, instr->RnMode());
+      const int32_t rn_val32 = get_wregister(rn, instr->RnMode());
+      const double vn_dbl = (instr->SFField() == 1)
+                                ? static_cast<double>(rn_val64)
+                                : static_cast<double>(rn_val32);
+      set_vregisterd(vd, 0, bit_cast<int64_t, double>(vn_dbl));
+      set_vregisterd(vd, 1, 0);
+    } else if (instr->Bits(16, 5) == 6) {
+      // Format(instr, "fmovrd'sf 'rd, 'vn");
+      const int64_t vn_val = get_vregisterd(vn, 0);
+      set_register(instr, rd, vn_val, R31IsZR);
+    } else if (instr->Bits(16, 5) == 7) {
+      // Format(instr, "fmovdr'sf 'vd, 'rn");
+      const int64_t rn_val = get_register(rn, R31IsZR);
+      set_vregisterd(vd, 0, rn_val);
+      set_vregisterd(vd, 1, 0);
+    } else if (instr->Bits(16, 5) == 24) {
+      // Format(instr, "fcvtzds'sf 'rd, 'vn");
+      const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
+      set_register(instr, rd, static_cast<int64_t>(vn_val), instr->RdMode());
+    } else {
+      UnimplementedInstruction(instr);
+    }
   } else {
     UnimplementedInstruction(instr);
   }