[arm, arm64] Implemented unaligned scalar float access.

runtime/vm/disassembler_arm64.cc

Index: runtime/vm/disassembler_arm64.cc
diff --git a/runtime/vm/disassembler_arm64.cc b/runtime/vm/disassembler_arm64.cc
index 448fda328ca7c3203add6a7da79a09de09df01b0..77bc20f40c44974d56d97b88858ba6db491ec5bd 100644
--- a/runtime/vm/disassembler_arm64.cc
+++ b/runtime/vm/disassembler_arm64.cc
@@ -1319,18 +1319,31 @@ void ARM64Decoder::DecodeFPImm(Instr* instr) {
 
 
 void ARM64Decoder::DecodeFPIntCvt(Instr* instr) {
-  if ((instr->Bit(29) != 0) || (instr->Bits(22, 2) != 1)) {
+  if ((instr->Bit(29) != 0)) {
     Unknown(instr);
     return;
   }
-  if (instr->Bits(16, 5) == 2) {
-    Format(instr, "scvtfd'sf 'vd, 'rn");
-  } else if (instr->Bits(16, 5) == 6) {
-    Format(instr, "fmovrd'sf 'rd, 'vn");
-  } else if (instr->Bits(16, 5) == 7) {
-    Format(instr, "fmovdr'sf 'vd, 'rn");
-  } else if (instr->Bits(16, 5) == 24) {
-    Format(instr, "fcvtzds'sf 'rd, 'vn");
+
+  if ((instr->SFField() == 0) && (instr->Bits(22, 2) == 0)) {
+    if (instr->Bits(16, 5) == 6) {
+      Format(instr, "fmovrs'sf 'rd, 'vn");
+    } else if (instr->Bits(16, 5) == 7) {
+      Format(instr, "fmovsr'sf 'vd, 'rn");
+    } else {
+      Unknown(instr);
+    }
+  } else if (instr->Bits(22, 2) == 1) {
+    if (instr->Bits(16, 5) == 2) {
+      Format(instr, "scvtfd'sf 'vd, 'rn");
+    } else if (instr->Bits(16, 5) == 6) {
+      Format(instr, "fmovrd'sf 'rd, 'vn");
+    } else if (instr->Bits(16, 5) == 7) {
+      Format(instr, "fmovdr'sf 'vd, 'rn");
+    } else if (instr->Bits(16, 5) == 24) {
+      Format(instr, "fcvtzds'sf 'rd, 'vn");
+    } else {
+      Unknown(instr);
+    }
   } else {
     Unknown(instr);
   }