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Issue 2940883008: [arm, arm64] Implemented unaligned scalar float access. (Closed)
Patch Set: piecewise float64 Created 3 years, 6 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
6 #if defined(TARGET_ARCH_ARM64) 6 #if defined(TARGET_ARCH_ARM64)
7 7
8 #include "vm/intermediate_language.h" 8 #include "vm/intermediate_language.h"
9 9
10 #include "vm/compiler.h" 10 #include "vm/compiler.h"
(...skipping 1109 matching lines...) Expand 10 before | Expand all | Expand 10 after
1120 1120
1121 if ((representation() == kUnboxedDouble) || 1121 if ((representation() == kUnboxedDouble) ||
1122 (representation() == kUnboxedFloat32x4) || 1122 (representation() == kUnboxedFloat32x4) ||
1123 (representation() == kUnboxedInt32x4) || 1123 (representation() == kUnboxedInt32x4) ||
1124 (representation() == kUnboxedFloat64x2)) { 1124 (representation() == kUnboxedFloat64x2)) {
1125 const VRegister result = locs()->out(0).fpu_reg(); 1125 const VRegister result = locs()->out(0).fpu_reg();
1126 switch (class_id()) { 1126 switch (class_id()) {
1127 ASSERT(aligned()); 1127 ASSERT(aligned());
1128 case kTypedDataFloat32ArrayCid: 1128 case kTypedDataFloat32ArrayCid:
1129 // Load single precision float. 1129 // Load single precision float.
1130 __ fldrs(result, element_address); 1130 if (aligned()) {
1131 __ fldrs(result, element_address);
1132 } else {
1133 __ LoadUnaligned(TMP, address, TMP2, kUnsignedWord);
1134 __ fmovsr(result, TMP);
1135 }
1131 break; 1136 break;
1132 case kTypedDataFloat64ArrayCid: 1137 case kTypedDataFloat64ArrayCid:
1133 // Load double precision float. 1138 // Load double precision float.
1134 __ fldrd(result, element_address); 1139 if (aligned()) {
1140 __ fldrd(result, element_address);
1141 } else {
1142 __ LoadUnaligned(TMP, address, TMP2, kDoubleWord);
1143 __ fmovdr(result, TMP);
1144 }
1135 break; 1145 break;
1136 case kTypedDataFloat64x2ArrayCid: 1146 case kTypedDataFloat64x2ArrayCid:
1137 case kTypedDataInt32x4ArrayCid: 1147 case kTypedDataInt32x4ArrayCid:
1138 case kTypedDataFloat32x4ArrayCid: 1148 case kTypedDataFloat32x4ArrayCid:
1149 ASSERT(aligned());
1139 __ fldrq(result, element_address); 1150 __ fldrq(result, element_address);
1140 break; 1151 break;
1141 default: 1152 default:
1142 UNREACHABLE(); 1153 UNREACHABLE();
1143 } 1154 }
1144 return; 1155 return;
1145 } 1156 }
1146 1157
1147 if ((representation() == kUnboxedInt32) || 1158 if ((representation() == kUnboxedInt32) ||
1148 (representation() == kUnboxedUint32)) { 1159 (representation() == kUnboxedUint32)) {
(...skipping 316 matching lines...) Expand 10 before | Expand all | Expand 10 after
1465 case kTypedDataUint32ArrayCid: { 1476 case kTypedDataUint32ArrayCid: {
1466 const Register value = locs()->in(2).reg(); 1477 const Register value = locs()->in(2).reg();
1467 if (aligned()) { 1478 if (aligned()) {
1468 __ str(value, element_address, kUnsignedWord); 1479 __ str(value, element_address, kUnsignedWord);
1469 } else { 1480 } else {
1470 __ StoreUnaligned(value, address, scratch, kUnsignedWord); 1481 __ StoreUnaligned(value, address, scratch, kUnsignedWord);
1471 } 1482 }
1472 break; 1483 break;
1473 } 1484 }
1474 case kTypedDataFloat32ArrayCid: { 1485 case kTypedDataFloat32ArrayCid: {
1475 ASSERT(aligned());
1476 const VRegister value_reg = locs()->in(2).fpu_reg(); 1486 const VRegister value_reg = locs()->in(2).fpu_reg();
1477 __ fstrs(value_reg, element_address); 1487 if (aligned()) {
1488 __ fstrs(value_reg, element_address);
1489 } else {
1490 __ fmovrs(TMP, value_reg);
1491 __ StoreUnaligned(TMP, address, scratch, kWord);
1492 }
1478 break; 1493 break;
1479 } 1494 }
1480 case kTypedDataFloat64ArrayCid: { 1495 case kTypedDataFloat64ArrayCid: {
1481 ASSERT(aligned());
1482 const VRegister value_reg = locs()->in(2).fpu_reg(); 1496 const VRegister value_reg = locs()->in(2).fpu_reg();
1483 __ fstrd(value_reg, element_address); 1497 if (aligned()) {
1498 __ fstrd(value_reg, element_address);
1499 } else {
1500 __ fmovrd(TMP, value_reg);
1501 __ StoreUnaligned(TMP, address, scratch, kDoubleWord);
1502 }
1484 break; 1503 break;
1485 } 1504 }
1486 case kTypedDataFloat64x2ArrayCid: 1505 case kTypedDataFloat64x2ArrayCid:
1487 case kTypedDataInt32x4ArrayCid: 1506 case kTypedDataInt32x4ArrayCid:
1488 case kTypedDataFloat32x4ArrayCid: { 1507 case kTypedDataFloat32x4ArrayCid: {
1489 ASSERT(aligned()); 1508 ASSERT(aligned());
1490 const VRegister value_reg = locs()->in(2).fpu_reg(); 1509 const VRegister value_reg = locs()->in(2).fpu_reg();
1491 __ fstrq(value_reg, element_address); 1510 __ fstrq(value_reg, element_address);
1492 break; 1511 break;
1493 } 1512 }
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6082 compiler->GenerateRuntimeCall(TokenPosition::kNoSource, deopt_id(), 6101 compiler->GenerateRuntimeCall(TokenPosition::kNoSource, deopt_id(),
6083 kGrowRegExpStackRuntimeEntry, 1, locs()); 6102 kGrowRegExpStackRuntimeEntry, 1, locs());
6084 __ Drop(1); 6103 __ Drop(1);
6085 __ Pop(result); 6104 __ Pop(result);
6086 } 6105 }
6087 6106
6088 6107
6089 } // namespace dart 6108 } // namespace dart
6090 6109
6091 #endif // defined TARGET_ARCH_ARM64 6110 #endif // defined TARGET_ARCH_ARM64
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