Beings adding SIMD support to arm64.

runtime/vm/intermediate_language_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/intermediate_language.h"
 
 #include "vm/cpu.h"
@@ skipping 60 matching lines @@
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   locs->set_in(0, Location::RegisterLocation(R0));
   return locs;
 }
 
 
 // Attempt optimized compilation at return instruction instead of at the entry.
 // The entry needs to be patchable, no inlined objects are allowed in the area
 // that will be overwritten by the patch instructions: a branch macro sequence.
 void ReturnInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register result = locs()->in(0).reg();
+  const Register result = locs()->in(0).reg();
   ASSERT(result == R0);
 #if defined(DEBUG)
   Label stack_ok;
   __ Comment("Stack Check");
   const intptr_t fp_sp_dist =
       (kFirstLocalSlotFromFp + 1 - compiler->StackSize()) * kWordSize;
   ASSERT(fp_sp_dist <= 0);
   __ sub(R2, SP, ShifterOperand(FP));
   __ CompareImmediate(R2, fp_sp_dist);
   __ b(&stack_ok, EQ);
@@ skipping 141 matching lines @@
 
 
 LocationSummary* LoadLocalInstr::MakeLocationSummary(bool opt) const {
   return LocationSummary::Make(0,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void LoadLocalInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
   __ LoadFromOffset(kWord, result, FP, local().index() * kWordSize);
 }
 
 
 LocationSummary* StoreLocalInstr::MakeLocationSummary(bool opt) const {
   return LocationSummary::Make(1,
                                Location::SameAsFirstInput(),
                                LocationSummary::kNoCall);
 }
 
 
 void StoreLocalInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register value = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   ASSERT(result == value);  // Assert that register assignment is correct.
   __ str(value, Address(FP, local().index() * kWordSize));
 }
 
 
 LocationSummary* ConstantInstr::MakeLocationSummary(bool opt) const {
   return LocationSummary::Make(0,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void ConstantInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   // The register allocator drops constant definitions that have no uses.
   if (!locs()->out(0).IsInvalid()) {
-    Register result = locs()->out(0).reg();
+    const Register result = locs()->out(0).reg();
     __ LoadObject(result, value());
   }
 }
 
 
 LocationSummary* UnboxedConstantInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 0;
   const intptr_t kNumTemps = 1;
   LocationSummary* locs =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
@@ skipping 63 matching lines @@
                                 kNonBoolTypeErrorRuntimeEntry,
                                 1,
                                 locs);
   // We should never return here.
   __ bkpt(0);
   __ Bind(&done);
 }
 
 
 void AssertBooleanInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register obj = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register obj = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
 
   EmitAssertBoolean(obj, token_pos(), deopt_id(), locs(), compiler);
   ASSERT(obj == result);
 }
 
 
 static Condition TokenKindToSmiCondition(Token::Kind kind) {
   switch (kind) {
     case Token::kEQ: return EQ;
     case Token::kNE: return NE;
@@ skipping 139 matching lines @@
       UNREACHABLE();
       return VS;
   }
 }
 
 
 static Condition EmitUnboxedMintEqualityOp(FlowGraphCompiler* compiler,
                                            LocationSummary* locs,
                                            Token::Kind kind) {
   ASSERT(Token::IsEqualityOperator(kind));
-  QRegister left = locs->in(0).fpu_reg();
-  QRegister right = locs->in(1).fpu_reg();
-  QRegister tmpq = locs->temp(0).fpu_reg();
-  Register tmp_lo = locs->temp(1).reg();
-  Register tmp_hi = locs->temp(2).reg();
+  const QRegister left = locs->in(0).fpu_reg();
+  const QRegister right = locs->in(1).fpu_reg();
+  const QRegister tmpq = locs->temp(0).fpu_reg();
+  const Register tmp_lo = locs->temp(1).reg();
+  const Register tmp_hi = locs->temp(2).reg();
 
   __ vceqqi(kWord, tmpq, left, right);
   __ vmovrrd(tmp_lo, tmp_hi, EvenDRegisterOf(tmpq));
   // tmp_lo and tmp_hi must both be 0xffffffff.
   __ and_(tmp_lo, tmp_lo, ShifterOperand(tmp_hi));
 
   Condition true_condition = TokenKindToMintCondition(kind);
   __ CompareImmediate(tmp_lo, 0xffffffff);
   return true_condition;
 }
 
 
 static Condition EmitUnboxedMintComparisonOp(FlowGraphCompiler* compiler,
                                              LocationSummary* locs,
                                              Token::Kind kind) {
-  QRegister left = locs->in(0).fpu_reg();
-  QRegister right = locs->in(1).fpu_reg();
-  DRegister dleft0 = EvenDRegisterOf(left);
-  DRegister dright0 = EvenDRegisterOf(right);
-  SRegister sleft0 = EvenSRegisterOf(dleft0);
-  SRegister sleft1 = OddSRegisterOf(dleft0);
-  SRegister sright0 = EvenSRegisterOf(dright0);
-  SRegister sright1 = OddSRegisterOf(dright0);
+  const QRegister left = locs->in(0).fpu_reg();
+  const QRegister right = locs->in(1).fpu_reg();
+  const DRegister dleft0 = EvenDRegisterOf(left);
+  const DRegister dright0 = EvenDRegisterOf(right);
+  const SRegister sleft0 = EvenSRegisterOf(dleft0);
+  const SRegister sleft1 = OddSRegisterOf(dleft0);
+  const SRegister sright0 = EvenSRegisterOf(dright0);
+  const SRegister sright1 = OddSRegisterOf(dright0);
 
-  Register tmp_left = locs->temp(0).reg();
-  Register tmp_right = locs->temp(1).reg();
+  const Register tmp_left = locs->temp(0).reg();
+  const Register tmp_right = locs->temp(1).reg();
 
   // 64-bit comparison
   Condition hi_true_cond, hi_false_cond, lo_false_cond;
   switch (kind) {
     case Token::kLT:
     case Token::kLTE:
       hi_true_cond = LT;
       hi_false_cond = GT;
       lo_false_cond = (kind == Token::kLT) ? CS : HI;
       break;
@@ skipping 43 matching lines @@
     default:
       UNREACHABLE();
       return VS;
   }
 }
 
 
 static Condition EmitDoubleComparisonOp(FlowGraphCompiler* compiler,
                                         LocationSummary* locs,
                                         Token::Kind kind) {
-  QRegister left = locs->in(0).fpu_reg();
-  QRegister right = locs->in(1).fpu_reg();
-  DRegister dleft = EvenDRegisterOf(left);
-  DRegister dright = EvenDRegisterOf(right);
+  const QRegister left = locs->in(0).fpu_reg();
+  const QRegister right = locs->in(1).fpu_reg();
+  const DRegister dleft = EvenDRegisterOf(left);
+  const DRegister dright = EvenDRegisterOf(right);
   __ vcmpd(dleft, dright);
   __ vmstat();
   Condition true_condition = TokenKindToDoubleCondition(kind);
   return true_condition;
 }
 
 
 Condition EqualityCompareInstr::EmitComparisonCode(FlowGraphCompiler* compiler,
                                                    BranchLabels labels) {
   if (operation_cid() == kSmiCid) {
     return EmitSmiComparisonOp(compiler, locs(), kind());
   } else if (operation_cid() == kMintCid) {
     return EmitUnboxedMintEqualityOp(compiler, locs(), kind());
   } else {
     ASSERT(operation_cid() == kDoubleCid);
     return EmitDoubleComparisonOp(compiler, locs(), kind());
   }
 }
 
 
 void EqualityCompareInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT((kind() == Token::kNE) || (kind() == Token::kEQ));
 
   // The ARM code does not use true- and false-labels here.
   BranchLabels labels = { NULL, NULL, NULL };
   Condition true_condition = EmitComparisonCode(compiler, labels);
 
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
   if ((operation_cid() == kSmiCid) || (operation_cid() == kMintCid)) {
     __ LoadObject(result, Bool::True(), true_condition);
     __ LoadObject(result, Bool::False(), NegateCondition(true_condition));
   } else {
     ASSERT(operation_cid() == kDoubleCid);
     Label done;
     __ LoadObject(result, Bool::False());
     if (true_condition != NE) {
       __ b(&done, VS);  // x == NaN -> false, x != NaN -> true.
     }
@@ skipping 27 matching lines @@
   locs->set_in(0, Location::RequiresRegister());
   // Only one input can be a constant operand. The case of two constant
   // operands should be handled by constant propagation.
   locs->set_in(1, Location::RegisterOrConstant(right()));
   return locs;
 }
 
 
 Condition TestSmiInstr::EmitComparisonCode(FlowGraphCompiler* compiler,
                                            BranchLabels labels) {
-  Register left = locs()->in(0).reg();
+  const Register left = locs()->in(0).reg();
   Location right = locs()->in(1);
   if (right.IsConstant()) {
     ASSERT(right.constant().IsSmi());
     const int32_t imm =
         reinterpret_cast<int32_t>(right.constant().raw());
     __ TestImmediate(left, imm);
   } else {
     __ tst(left, ShifterOperand(right.reg()));
   }
   Condition true_condition = (kind() == Token::kNE) ? NE : EQ;
@@ skipping 23 matching lines @@
   locs->set_in(0, Location::RequiresRegister());
   locs->set_temp(0, Location::RequiresRegister());
   locs->set_out(0, Location::RequiresRegister());
   return locs;
 }
 
 
 Condition TestCidsInstr::EmitComparisonCode(FlowGraphCompiler* compiler,
                                             BranchLabels labels) {
   ASSERT((kind() == Token::kIS) || (kind() == Token::kISNOT));
-  Register val_reg = locs()->in(0).reg();
-  Register cid_reg = locs()->temp(0).reg();
+  const Register val_reg = locs()->in(0).reg();
+  const Register cid_reg = locs()->temp(0).reg();
 
   Label* deopt = CanDeoptimize() ?
       compiler->AddDeoptStub(deopt_id(), ICData::kDeoptTestCids) : NULL;
 
   const intptr_t true_result = (kind() == Token::kIS) ? 1 : 0;
   const ZoneGrowableArray<intptr_t>& data = cid_results();
   ASSERT(data[0] == kSmiCid);
   bool result = data[1] == true_result;
   __ tst(val_reg, ShifterOperand(kSmiTagMask));
   __ b(result ? labels.true_label : labels.false_label, EQ);
@@ skipping 22 matching lines @@
 
 
 void TestCidsInstr::EmitBranchCode(FlowGraphCompiler* compiler,
                                    BranchInstr* branch) {
   BranchLabels labels = compiler->CreateBranchLabels(branch);
   EmitComparisonCode(compiler, labels);
 }
 
 
 void TestCidsInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register result_reg = locs()->out(0).reg();
+  const Register result_reg = locs()->out(0).reg();
   Label is_true, is_false, done;
   BranchLabels labels = { &is_true, &is_false, &is_false };
   EmitComparisonCode(compiler, labels);
   __ Bind(&is_false);
   __ LoadObject(result_reg, Bool::False());
   __ b(&done);
   __ Bind(&is_true);
   __ LoadObject(result_reg, Bool::True());
   __ Bind(&done);
 }
@@ skipping 46 matching lines @@
     return EmitDoubleComparisonOp(compiler, locs(), kind());
   }
 }
 
 
 void RelationalOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   // The ARM code does not use true- and false-labels here.
   BranchLabels labels = { NULL, NULL, NULL };
   Condition true_condition = EmitComparisonCode(compiler, labels);
 
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
   if (operation_cid() == kSmiCid) {
     __ LoadObject(result, Bool::True(), true_condition);
     __ LoadObject(result, Bool::False(), NegateCondition(true_condition));
   } else if (operation_cid() == kMintCid) {
-    Register cr = locs()->temp(0).reg();
+    const Register cr = locs()->temp(0).reg();
     __ LoadObject(result, Bool::True());
     __ CompareImmediate(cr, 1);
     __ LoadObject(result, Bool::False(), NE);
   } else {
     ASSERT(operation_cid() == kDoubleCid);
     Label done;
     __ LoadObject(result, Bool::False());
     if (true_condition != NE) {
       __ b(&done, VS);  // x == NaN -> false, x != NaN -> true.
     }
     __ LoadObject(result, Bool::True(), true_condition);
     __ Bind(&done);
   }
 }
 
 
 void RelationalOpInstr::EmitBranchCode(FlowGraphCompiler* compiler,
                                        BranchInstr* branch) {
   BranchLabels labels = compiler->CreateBranchLabels(branch);
   Condition true_condition = EmitComparisonCode(compiler, labels);
 
   if (operation_cid() == kSmiCid) {
     EmitBranchOnCondition(compiler, true_condition, labels);
   } else if (operation_cid() == kMintCid) {
-    Register result = locs()->temp(0).reg();
+    const Register result = locs()->temp(0).reg();
     __ CompareImmediate(result, 1);
     __ b(labels.true_label, EQ);
     __ b(labels.false_label, NE);
   } else if (operation_cid() == kDoubleCid) {
     Label* nan_result = (true_condition == NE) ?
         labels.true_label : labels.false_label;
     __ b(nan_result, VS);
     EmitBranchOnCondition(compiler, true_condition, labels);
   }
 }
 
 
 LocationSummary* NativeCallInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 0;
   const intptr_t kNumTemps = 3;
   LocationSummary* locs =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kCall);
   locs->set_temp(0, Location::RegisterLocation(R1));
   locs->set_temp(1, Location::RegisterLocation(R2));
   locs->set_temp(2, Location::RegisterLocation(R5));
   locs->set_out(0, Location::RegisterLocation(R0));
   return locs;
 }
 
 
 void NativeCallInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT(locs()->temp(0).reg() == R1);
   ASSERT(locs()->temp(1).reg() == R2);
   ASSERT(locs()->temp(2).reg() == R5);
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
 
   // Push the result place holder initialized to NULL.
   __ PushObject(Object::ZoneHandle());
   // Pass a pointer to the first argument in R2.
   if (!function().HasOptionalParameters()) {
     __ AddImmediate(R2, FP, (kParamEndSlotFromFp +
                              function().NumParameters()) * kWordSize);
   } else {
     __ AddImmediate(R2, FP, kFirstLocalSlotFromFp * kWordSize);
   }
@@ skipping 33 matching lines @@
 LocationSummary* StringFromCharCodeInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   // TODO(fschneider): Allow immediate operands for the char code.
   return LocationSummary::Make(kNumInputs,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void StringFromCharCodeInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register char_code = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register char_code = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   __ LoadImmediate(result,
                    reinterpret_cast<uword>(Symbols::PredefinedAddress()));
   __ AddImmediate(result, Symbols::kNullCharCodeSymbolOffset * kWordSize);
   __ ldr(result, Address(result, char_code, LSL, 1));  // Char code is a smi.
 }
 
 
 LocationSummary* StringToCharCodeInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   return LocationSummary::Make(kNumInputs,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void StringToCharCodeInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT(cid_ == kOneByteStringCid);
-  Register str = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register str = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   __ ldr(result, FieldAddress(str, String::length_offset()));
   __ cmp(result, ShifterOperand(Smi::RawValue(1)));
   __ LoadImmediate(result, -1, NE);
   __ ldrb(result, FieldAddress(str, OneByteString::data_offset()), EQ);
   __ SmiTag(result);
 }
 
 
 LocationSummary* StringInterpolateInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kCall);
   summary->set_in(0, Location::RegisterLocation(R0));
   summary->set_out(0, Location::RegisterLocation(R0));
   return summary;
 }
 
 
 void StringInterpolateInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register array = locs()->in(0).reg();
+  const Register array = locs()->in(0).reg();
   __ Push(array);
   const int kNumberOfArguments = 1;
   const Array& kNoArgumentNames = Object::null_array();
   compiler->GenerateStaticCall(deopt_id(),
                                token_pos(),
                                CallFunction(),
                                kNumberOfArguments,
                                kNoArgumentNames,
                                locs());
   ASSERT(locs()->out(0).reg() == R0);
 }
 
 
 LocationSummary* LoadUntaggedInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   return LocationSummary::Make(kNumInputs,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void LoadUntaggedInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register object = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register object = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   __ LoadFromOffset(kWord, result, object, offset() - kHeapObjectTag);
 }
 
 
 LocationSummary* LoadClassIdInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   return LocationSummary::Make(kNumInputs,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void LoadClassIdInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register object = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register object = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   Label load, done;
   __ tst(object, ShifterOperand(kSmiTagMask));
   __ b(&load, NE);
   __ LoadImmediate(result, Smi::RawValue(kSmiCid));
   __ b(&done);
   __ Bind(&load);
   __ LoadClassId(result, object);
   __ SmiTag(result);
   __ Bind(&done);
 }
@@ skipping 108 matching lines @@
   return locs;
 }
 
 
 void LoadIndexedInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if ((representation() == kUnboxedDouble)    ||
       (representation() == kUnboxedMint)      ||
       (representation() == kUnboxedFloat32x4) ||
       (representation() == kUnboxedInt32x4)   ||
       (representation() == kUnboxedFloat64x2)) {
-    Register array = locs()->in(0).reg();
-    Register idx = locs()->in(1).reg();
+    const Register array = locs()->in(0).reg();
+    const Register idx = locs()->in(1).reg();
     switch (index_scale()) {
       case 1:
         __ add(idx, array, ShifterOperand(idx, ASR, kSmiTagSize));
         break;
       case 4:
         __ add(idx, array, ShifterOperand(idx, LSL, 1));
         break;
       case 8:
         __ add(idx, array, ShifterOperand(idx, LSL, 2));
         break;
@@ skipping 41 matching lines @@
         break;
       case kTypedDataFloat64x2ArrayCid:
       case kTypedDataInt32x4ArrayCid:
       case kTypedDataFloat32x4ArrayCid:
         __ vldmd(IA, idx, dresult0, 2);
         break;
     }
     return;
   }
 
-  Register array = locs()->in(0).reg();
+  const Register array = locs()->in(0).reg();
   Location index = locs()->in(1);
   ASSERT(index.IsRegister());  // TODO(regis): Revisit.
   Address element_address(kNoRegister, 0);
   // Note that index is expected smi-tagged, (i.e, times 2) for all arrays
   // with index scale factor > 1. E.g., for Uint8Array and OneByteString the
   // index is expected to be untagged before accessing.
   ASSERT(kSmiTagShift == 1);
   const intptr_t offset = IsExternal()
       ? 0
       : FlowGraphCompiler::DataOffsetFor(class_id()) - kHeapObjectTag;
@@ skipping 17 matching lines @@
     case 4: {
       __ add(index.reg(), array, ShifterOperand(index.reg(), LSL, 1));
       element_address = Address(index.reg(), offset);
       break;
     }
     // Cases 8 and 16 are only for unboxed values and are handled above.
     default:
       UNREACHABLE();
   }
 
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
   switch (class_id()) {
     case kTypedDataInt8ArrayCid:
       ASSERT(index_scale() == 1);
       __ ldrsb(result, element_address);
       __ SmiTag(result);
       break;
     case kTypedDataUint8ArrayCid:
     case kTypedDataUint8ClampedArrayCid:
     case kExternalTypedDataUint8ArrayCid:
     case kExternalTypedDataUint8ClampedArrayCid:
@@ skipping 126 matching lines @@
   return locs;
 }
 
 
 void StoreIndexedInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if ((class_id() == kTypedDataFloat32ArrayCid) ||
       (class_id() == kTypedDataFloat64ArrayCid) ||
       (class_id() == kTypedDataFloat32x4ArrayCid) ||
       (class_id() == kTypedDataFloat64x2ArrayCid) ||
       (class_id() == kTypedDataInt32x4ArrayCid)) {
-    Register array = locs()->in(0).reg();
-    Register idx = locs()->in(1).reg();
+    const Register array = locs()->in(0).reg();
+    const Register idx = locs()->in(1).reg();
     Location value = locs()->in(2);
     switch (index_scale()) {
       case 1:
         __ add(idx, array, ShifterOperand(idx, ASR, kSmiTagSize));
         break;
       case 4:
         __ add(idx, array, ShifterOperand(idx, LSL, 1));
         break;
       case 8:
         __ add(idx, array, ShifterOperand(idx, LSL, 2));
         break;
       case 16:
         __ add(idx, array, ShifterOperand(idx, LSL, 3));
         break;
       default:
         // Case 2 is not reachable: We don't have unboxed 16-bit sized loads.
         UNREACHABLE();
     }
     if (!IsExternal()) {
       ASSERT(this->array()->definition()->representation() == kTagged);
       __ AddImmediate(idx,
           FlowGraphCompiler::DataOffsetFor(class_id()) - kHeapObjectTag);
     }
     switch (class_id()) {
       case kTypedDataFloat32ArrayCid: {
-        SRegister value_reg =
+        const SRegister value_reg =
             EvenSRegisterOf(EvenDRegisterOf(value.fpu_reg()));
         __ StoreSToOffset(value_reg, idx, 0);
         break;
       }
       case kTypedDataFloat64ArrayCid: {
-        DRegister value_reg = EvenDRegisterOf(value.fpu_reg());
+        const DRegister value_reg = EvenDRegisterOf(value.fpu_reg());
         __ StoreDToOffset(value_reg, idx, 0);
         break;
       }
       case kTypedDataFloat64x2ArrayCid:
       case kTypedDataInt32x4ArrayCid:
       case kTypedDataFloat32x4ArrayCid: {
         const DRegister value_reg = EvenDRegisterOf(value.fpu_reg());
         __ vstmd(IA, idx, value_reg, 2);
         break;
       }
       default:
         UNREACHABLE();
     }
     return;
   }
 
-  Register array = locs()->in(0).reg();
+  const Register array = locs()->in(0).reg();
   Location index = locs()->in(1);
 
   Address element_address(kNoRegister, 0);
   ASSERT(index.IsRegister());  // TODO(regis): Revisit.
   // Note that index is expected smi-tagged, (i.e, times 2) for all arrays
   // with index scale factor > 1. E.g., for Uint8Array and OneByteString the
   // index is expected to be untagged before accessing.
   ASSERT(kSmiTagShift == 1);
   const intptr_t offset = IsExternal()
       ? 0
@@ skipping 20 matching lines @@
       break;
     }
     // Cases 8 and 16 are only for unboxed values and are handled above.
     default:
       UNREACHABLE();
   }
 
   switch (class_id()) {
     case kArrayCid:
       if (ShouldEmitStoreBarrier()) {
-        Register value = locs()->in(2).reg();
+        const Register value = locs()->in(2).reg();
         __ StoreIntoObject(array, element_address, value);
       } else if (locs()->in(2).IsConstant()) {
         const Object& constant = locs()->in(2).constant();
         __ StoreIntoObjectNoBarrier(array, element_address, constant);
       } else {
-        Register value = locs()->in(2).reg();
+        const Register value = locs()->in(2).reg();
         __ StoreIntoObjectNoBarrier(array, element_address, value);
       }
       break;
     case kTypedDataInt8ArrayCid:
     case kTypedDataUint8ArrayCid:
     case kExternalTypedDataUint8ArrayCid:
     case kOneByteStringCid: {
       if (locs()->in(2).IsConstant()) {
         const Smi& constant = Smi::Cast(locs()->in(2).constant());
         __ LoadImmediate(IP, static_cast<int8_t>(constant.Value()));
         __ strb(IP, element_address);
       } else {
-        Register value = locs()->in(2).reg();
+        const Register value = locs()->in(2).reg();
         __ SmiUntag(value);
         __ strb(value, element_address);
       }
       break;
     }
     case kTypedDataUint8ClampedArrayCid:
     case kExternalTypedDataUint8ClampedArrayCid: {
       if (locs()->in(2).IsConstant()) {
         const Smi& constant = Smi::Cast(locs()->in(2).constant());
         intptr_t value = constant.Value();
         // Clamp to 0x0 or 0xFF respectively.
         if (value > 0xFF) {
           value = 0xFF;
         } else if (value < 0) {
           value = 0;
         }
         __ LoadImmediate(IP, static_cast<int8_t>(value));
         __ strb(IP, element_address);
       } else {
-        Register value = locs()->in(2).reg();
+        const Register value = locs()->in(2).reg();
         Label store_value;
         __ SmiUntag(value);
         __ cmp(value, ShifterOperand(0xFF));
         // Clamp to 0x00 or 0xFF respectively.
         __ b(&store_value, LS);
         __ mov(value, ShifterOperand(0x00), LE);
         __ mov(value, ShifterOperand(0xFF), GT);
         __ Bind(&store_value);
         __ strb(value, element_address);
       }
       break;
     }
     case kTypedDataInt16ArrayCid:
     case kTypedDataUint16ArrayCid: {
-      Register value = locs()->in(2).reg();
+      const Register value = locs()->in(2).reg();
       __ SmiUntag(value);
       __ strh(value, element_address);
       break;
     }
     case kTypedDataInt32ArrayCid:
     case kTypedDataUint32ArrayCid: {
       if (value()->IsSmiValue()) {
         ASSERT(RequiredInputRepresentation(2) == kTagged);
-        Register value = locs()->in(2).reg();
+        const Register value = locs()->in(2).reg();
         __ SmiUntag(value);
         __ str(value, element_address);
       } else {
         ASSERT(RequiredInputRepresentation(2) == kUnboxedMint);
-        QRegister value = locs()->in(2).fpu_reg();
+        const QRegister value = locs()->in(2).fpu_reg();
         ASSERT(value == Q7);
         __ vmovrs(TMP, EvenSRegisterOf(EvenDRegisterOf(value)));
         __ str(TMP, element_address);
       }
       break;
     }
     default:
       UNREACHABLE();
   }
 }
@@ skipping 28 matching lines @@
     ASSERT(field().is_final());
   }
 
   if (field_cid == kDynamicCid) {
     ASSERT(!compiler->is_optimizing());
     return;  // Nothing to emit.
   }
 
   const intptr_t value_cid = value()->Type()->ToCid();
 
-  Register value_reg = locs()->in(0).reg();
+  const Register value_reg = locs()->in(0).reg();
 
-  Register value_cid_reg = locs()->temp(0).reg();
+  const Register value_cid_reg = locs()->temp(0).reg();
 
-  Register temp_reg = locs()->temp(1).reg();
+  const Register temp_reg = locs()->temp(1).reg();
 
   Register field_reg = needs_field_temp_reg ?
       locs()->temp(locs()->temp_count() - 1).reg() : kNoRegister;
 
   Label ok, fail_label;
 
   Label* deopt = compiler->is_optimizing() ?
       compiler->AddDeoptStub(deopt_id(), ICData::kDeoptGuardField) : NULL;
 
   Label* fail = (deopt != NULL) ? deopt : &fail_label;
@@ skipping 328 matching lines @@
                        ? Location::WritableRegister()
                        : Location::RegisterOrConstant(value()));
   }
   return summary;
 }
 
 
 void StoreInstanceFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Label skip_store;
 
-  Register instance_reg = locs()->in(0).reg();
+  const Register instance_reg = locs()->in(0).reg();
 
   if (IsUnboxedStore() && compiler->is_optimizing()) {
     const DRegister value = EvenDRegisterOf(locs()->in(1).fpu_reg());
     const Register temp = locs()->temp(0).reg();
     const Register temp2 = locs()->temp(1).reg();
     const intptr_t cid = field().UnboxedFieldCid();
 
     if (is_initialization_) {
       const Class* cls = NULL;
       switch (cid) {
@@ skipping 164 matching lines @@
                          temp2);
       __ Bind(&copy_float64x2);
       __ CopyFloat64x2Field(temp, value_reg, TMP, temp2, fpu_temp);
       __ b(&skip_store);
     }
 
     __ Bind(&store_pointer);
   }
 
   if (ShouldEmitStoreBarrier()) {
-    Register value_reg = locs()->in(1).reg();
+    const Register value_reg = locs()->in(1).reg();
     __ StoreIntoObject(instance_reg,
                        FieldAddress(instance_reg, offset_in_bytes_),
                        value_reg,
                        CanValueBeSmi());
   } else {
     if (locs()->in(1).IsConstant()) {
       __ StoreIntoObjectNoBarrier(
           instance_reg,
           FieldAddress(instance_reg, offset_in_bytes_),
           locs()->in(1).constant());
     } else {
-      Register value_reg = locs()->in(1).reg();
+      const Register value_reg = locs()->in(1).reg();
       __ StoreIntoObjectNoBarrier(instance_reg,
           FieldAddress(instance_reg, offset_in_bytes_), value_reg);
     }
   }
   __ Bind(&skip_store);
 }
 
 
 LocationSummary* LoadStaticFieldInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresRegister());
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 // When the parser is building an implicit static getter for optimization,
 // it can generate a function body where deoptimization ids do not line up
 // with the unoptimized code.
 //
 // This is safe only so long as LoadStaticFieldInstr cannot deoptimize.
 void LoadStaticFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register field = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register field = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   __ LoadFromOffset(kWord, result,
                     field, Field::value_offset() - kHeapObjectTag);
 }
 
 
 LocationSummary* StoreStaticFieldInstr::MakeLocationSummary(bool opt) const {
   LocationSummary* locs = new LocationSummary(1, 1, LocationSummary::kNoCall);
   locs->set_in(0, value()->NeedsStoreBuffer() ? Location::WritableRegister()
                                               : Location::RequiresRegister());
   locs->set_temp(0, Location::RequiresRegister());
   return locs;
 }
 
 
 void StoreStaticFieldInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
-  Register temp = locs()->temp(0).reg();
+  const Register value = locs()->in(0).reg();
+  const Register temp = locs()->temp(0).reg();
 
   __ LoadObject(temp, field());
   if (this->value()->NeedsStoreBuffer()) {
     __ StoreIntoObject(temp,
         FieldAddress(temp, Field::value_offset()), value, CanValueBeSmi());
   } else {
     __ StoreIntoObjectNoBarrier(
         temp, FieldAddress(temp, Field::value_offset()), value);
   }
 }
@@ skipping 294 matching lines @@
         __ LoadMultipleDFromOffset(result, 2, temp,
             Float64x2::value_offset() - kHeapObjectTag);
         break;
       default:
         UNREACHABLE();
     }
     return;
   }
 
   Label done;
-  Register result_reg = locs()->out(0).reg();
+  const Register result_reg = locs()->out(0).reg();
   if (IsPotentialUnboxedLoad()) {
     const DRegister value = EvenDRegisterOf(locs()->temp(0).fpu_reg());
     const Register temp = locs()->temp(1).reg();
     const Register temp2 = locs()->temp(2).reg();
 
     Label load_pointer;
     Label load_double;
     Label load_float32x4;
     Label load_float64x2;
 
@@ skipping 84 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* locs =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kCall);
   locs->set_in(0, Location::RegisterLocation(R0));
   locs->set_out(0, Location::RegisterLocation(R0));
   return locs;
 }
 
 
 void InstantiateTypeInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register instantiator_reg = locs()->in(0).reg();
-  Register result_reg = locs()->out(0).reg();
+  const Register instantiator_reg = locs()->in(0).reg();
+  const Register result_reg = locs()->out(0).reg();
 
   // 'instantiator_reg' is the instantiator TypeArguments object (or null).
   // A runtime call to instantiate the type is required.
   __ PushObject(Object::ZoneHandle());  // Make room for the result.
   __ PushObject(type());
   __ Push(instantiator_reg);  // Push instantiator type arguments.
   compiler->GenerateRuntimeCall(token_pos(),
                                 deopt_id(),
                                 kInstantiateTypeRuntimeEntry,
                                 2,
@@ skipping 11 matching lines @@
   LocationSummary* locs =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kCall);
   locs->set_in(0, Location::RegisterLocation(R0));
   locs->set_out(0, Location::RegisterLocation(R0));
   return locs;
 }
 
 
 void InstantiateTypeArgumentsInstr::EmitNativeCode(
     FlowGraphCompiler* compiler) {
-  Register instantiator_reg = locs()->in(0).reg();
-  Register result_reg = locs()->out(0).reg();
+  const Register instantiator_reg = locs()->in(0).reg();
+  const Register result_reg = locs()->out(0).reg();
   ASSERT(instantiator_reg == R0);
   ASSERT(instantiator_reg == result_reg);
 
   // 'instantiator_reg' is the instantiator TypeArguments object (or null).
   ASSERT(!type_arguments().IsUninstantiatedIdentity() &&
          !type_arguments().CanShareInstantiatorTypeArguments(
              instantiator_class()));
   // If the instantiator is null and if the type argument vector
   // instantiated from null becomes a vector of dynamic, then use null as
   // the type arguments.
@@ skipping 70 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* locs =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kCall);
   locs->set_in(0, Location::RegisterLocation(R0));
   locs->set_out(0, Location::RegisterLocation(R0));
   return locs;
 }
 
 
 void CloneContextInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register context_value = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register context_value = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
 
   __ PushObject(Object::ZoneHandle());  // Make room for the result.
   __ Push(context_value);
   compiler->GenerateRuntimeCall(token_pos(),
                                 deopt_id(),
                                 kCloneContextRuntimeEntry,
                                 1,
                                 locs());
   __ Drop(1);  // Remove argument.
   __ Pop(result);  // Get result (cloned context).
@@ skipping 50 matching lines @@
 
 
 class CheckStackOverflowSlowPath : public SlowPathCode {
  public:
   explicit CheckStackOverflowSlowPath(CheckStackOverflowInstr* instruction)
       : instruction_(instruction) { }
 
   virtual void EmitNativeCode(FlowGraphCompiler* compiler) {
     if (FLAG_use_osr) {
       uword flags_address = Isolate::Current()->stack_overflow_flags_address();
-      Register value = instruction_->locs()->temp(0).reg();
+      const Register value = instruction_->locs()->temp(0).reg();
       __ Comment("CheckStackOverflowSlowPathOsr");
       __ Bind(osr_entry_label());
       __ LoadImmediate(IP, flags_address);
       __ LoadImmediate(value, Isolate::kOsrRequest);
       __ str(value, Address(IP));
     }
     __ Comment("CheckStackOverflowSlowPath");
     __ Bind(entry_label());
     compiler->SaveLiveRegisters(instruction_->locs());
     // pending_deoptimization_env_ is needed to generate a runtime call that
@@ skipping 31 matching lines @@
 
 void CheckStackOverflowInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   CheckStackOverflowSlowPath* slow_path = new CheckStackOverflowSlowPath(this);
   compiler->AddSlowPathCode(slow_path);
 
   __ LoadImmediate(IP, Isolate::Current()->stack_limit_address());
   __ ldr(IP, Address(IP));
   __ cmp(SP, ShifterOperand(IP));
   __ b(slow_path->entry_label(), LS);
   if (compiler->CanOSRFunction() && in_loop()) {
-    Register temp = locs()->temp(0).reg();
+    const Register temp = locs()->temp(0).reg();
     // In unoptimized code check the usage counter to trigger OSR at loop
     // stack checks.  Use progressively higher thresholds for more deeply
     // nested loops to attempt to hit outer loops with OSR when possible.
     __ LoadObject(temp, compiler->parsed_function().function());
     intptr_t threshold =
         FLAG_optimization_counter_threshold * (loop_depth() + 1);
     __ ldr(temp, FieldAddress(temp, Function::usage_counter_offset()));
     __ CompareImmediate(temp, threshold);
     __ b(slow_path->osr_entry_label(), GE);
   }
   if (compiler->ForceSlowPathForStackOverflow()) {
     __ b(slow_path->entry_label());
   }
   __ Bind(slow_path->exit_label());
 }
 
 
 static void EmitSmiShiftLeft(FlowGraphCompiler* compiler,
                              BinarySmiOpInstr* shift_left) {
   const bool is_truncating = shift_left->is_truncating();
   const LocationSummary& locs = *shift_left->locs();
-  Register left = locs.in(0).reg();
-  Register result = locs.out(0).reg();
+  const Register left = locs.in(0).reg();
+  const Register result = locs.out(0).reg();
   Label* deopt = shift_left->CanDeoptimize() ?
       compiler->AddDeoptStub(shift_left->deopt_id(), ICData::kDeoptBinarySmiOp)
       : NULL;
   if (locs.in(1).IsConstant()) {
     const Object& constant = locs.in(1).constant();
     ASSERT(constant.IsSmi());
     // Immediate shift operation takes 5 bits for the count.
     const intptr_t kCountLimit = 0x1F;
     const intptr_t value = Smi::Cast(constant).Value();
     if (value == 0) {
@@ skipping 14 matching lines @@
         __ cmp(left, ShifterOperand(IP, ASR, value));
         __ b(deopt, NE);  // Overflow.
       }
       // Shift for result now we know there is no overflow.
       __ Lsl(result, left, value);
     }
     return;
   }
 
   // Right (locs.in(1)) is not constant.
-  Register right = locs.in(1).reg();
+  const Register right = locs.in(1).reg();
   Range* right_range = shift_left->right()->definition()->range();
   if (shift_left->left()->BindsToConstant() && !is_truncating) {
     // TODO(srdjan): Implement code below for is_truncating().
     // If left is constant, we know the maximal allowed size for right.
     const Object& obj = shift_left->left()->BoundConstant();
     if (obj.IsSmi()) {
       const intptr_t left_int = Smi::Cast(obj).Value();
       if (left_int == 0) {
         __ cmp(right, ShifterOperand(0));
         __ b(deopt, MI);
@@ skipping 41 matching lines @@
     if (right_needs_check) {
       ASSERT(shift_left->CanDeoptimize());
       __ cmp(right,
              ShifterOperand(reinterpret_cast<int32_t>(Smi::New(Smi::kBits))));
       __ b(deopt, CS);
     }
     // Left is not a constant.
     // Check if count too large for handling it inlined.
     __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
     // Overflow test (preserve left, right, and IP);
-    Register temp = locs.temp(0).reg();
+    const Register temp = locs.temp(0).reg();
     __ Lsl(temp, left, IP);
     __ cmp(left, ShifterOperand(temp, ASR, IP));
     __ b(deopt, NE);  // Overflow.
     // Shift for result now we know there is no overflow.
     __ Lsl(result, left, IP);
   }
 }
 
 
 LocationSummary* BinarySmiOpInstr::MakeLocationSummary(bool opt) const {
@@ skipping 41 matching lines @@
 }
 
 
 void BinarySmiOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if (op_kind() == Token::kSHL) {
     EmitSmiShiftLeft(compiler, this);
     return;
   }
 
   ASSERT(!is_truncating());
-  Register left = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register left = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   Label* deopt = NULL;
   if (CanDeoptimize()) {
     deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptBinarySmiOp);
   }
 
   if (locs()->in(1).IsConstant()) {
     const Object& constant = locs()->in(1).constant();
     ASSERT(constant.IsSmi());
     const int32_t imm = reinterpret_cast<int32_t>(constant.raw());
     switch (op_kind()) {
@@ skipping 65 matching lines @@
           __ b(deopt, EQ);
           __ rsb(result, left, ShifterOperand(0));
           break;
         }
         ASSERT(Utils::IsPowerOfTwo(Utils::Abs(value)));
         const intptr_t shift_count =
             Utils::ShiftForPowerOfTwo(Utils::Abs(value)) + kSmiTagSize;
         ASSERT(kSmiTagSize == 1);
         __ mov(IP, ShifterOperand(left, ASR, 31));
         ASSERT(shift_count > 1);  // 1, -1 case handled above.
-        Register temp = locs()->temp(0).reg();
+        const Register temp = locs()->temp(0).reg();
         __ add(temp, left, ShifterOperand(IP, LSR, 32 - shift_count));
         ASSERT(shift_count > 0);
         __ mov(result, ShifterOperand(temp, ASR, shift_count));
         if (value < 0) {
           __ rsb(result, result, ShifterOperand(0));
         }
         __ SmiTag(result);
         break;
       }
       case Token::kBIT_AND: {
@@ skipping 56 matching lines @@
         break;
       }
 
       default:
         UNREACHABLE();
         break;
     }
     return;
   }
 
-  Register right = locs()->in(1).reg();
+  const Register right = locs()->in(1).reg();
   Range* right_range = this->right()->definition()->range();
   switch (op_kind()) {
     case Token::kADD: {
       if (deopt == NULL) {
         __ add(result, left, ShifterOperand(right));
       } else {
         __ adds(result, left, ShifterOperand(right));
         __ b(deopt, VS);
       }
       break;
@@ skipping 41 matching lines @@
       // No overflow check.
       __ eor(result, left, ShifterOperand(right));
       break;
     }
     case Token::kTRUNCDIV: {
       if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
         // Handle divide by zero in runtime.
         __ cmp(right, ShifterOperand(0));
         __ b(deopt, EQ);
       }
-      Register temp = locs()->temp(0).reg();
-      DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+      const Register temp = locs()->temp(0).reg();
+      const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
       __ Asr(temp, left, kSmiTagSize);  // SmiUntag left into temp.
       __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
 
       __ IntegerDivide(result, temp, IP, dtemp, DTMP);
 
       // Check the corner case of dividing the 'MIN_SMI' with -1, in which
       // case we cannot tag the result.
       __ CompareImmediate(result, 0x40000000);
       __ b(deopt, EQ);
       __ SmiTag(result);
       break;
     }
     case Token::kMOD: {
       if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
         // Handle divide by zero in runtime.
         __ cmp(right, ShifterOperand(0));
         __ b(deopt, EQ);
       }
-      Register temp = locs()->temp(0).reg();
-      DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+      const Register temp = locs()->temp(0).reg();
+      const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
       __ Asr(temp, left, kSmiTagSize);  // SmiUntag left into temp.
       __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
 
       __ IntegerDivide(result, temp, IP, dtemp, DTMP);
 
       __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
       __ mls(result, IP, result, temp);  // result <- left - right * result
       __ SmiTag(result);
       //  res = left % right;
       //  if (res < 0) {
@@ skipping 19 matching lines @@
         __ b(deopt, LT);
       }
       __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
       // sarl operation masks the count to 5 bits.
       const intptr_t kCountLimit = 0x1F;
       if ((right_range == NULL) ||
           !right_range->IsWithin(RangeBoundary::kMinusInfinity, kCountLimit)) {
         __ CompareImmediate(IP, kCountLimit);
         __ LoadImmediate(IP, kCountLimit, GT);
       }
-      Register temp = locs()->temp(0).reg();
+      const Register temp = locs()->temp(0).reg();
       __ Asr(temp, left, kSmiTagSize);  // SmiUntag left into temp.
       __ Asr(result, temp, IP);
       __ SmiTag(result);
       break;
     }
     case Token::kDIV: {
       // Dispatches to 'Double./'.
       // TODO(srdjan): Implement as conversion to double and double division.
       UNREACHABLE();
       break;
@@ skipping 24 matching lines @@
   summary->set_in(1, Location::RequiresRegister());
   return summary;
 }
 
 
 void CheckEitherNonSmiInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Label* deopt = compiler->AddDeoptStub(deopt_id(),
                                         ICData::kDeoptBinaryDoubleOp);
   intptr_t left_cid = left()->Type()->ToCid();
   intptr_t right_cid = right()->Type()->ToCid();
-  Register left = locs()->in(0).reg();
-  Register right = locs()->in(1).reg();
+  const Register left = locs()->in(0).reg();
+  const Register right = locs()->in(1).reg();
   if (this->left()->definition() == this->right()->definition()) {
     __ tst(left, ShifterOperand(kSmiTagMask));
   } else if (left_cid == kSmiCid) {
     __ tst(right, ShifterOperand(kSmiTagMask));
   } else if (right_cid == kSmiCid) {
     __ tst(left, ShifterOperand(kSmiTagMask));
   } else {
     __ orr(IP, left, ShifterOperand(right));
     __ tst(IP, ShifterOperand(kSmiTagMask));
   }
@@ skipping 56 matching lines @@
 
   if (value_cid == kDoubleCid) {
     __ LoadDFromOffset(result, value, Double::value_offset() - kHeapObjectTag);
   } else if (value_cid == kSmiCid) {
     __ SmiUntag(value);  // Untag input before conversion.
     __ vmovsr(STMP, value);
     __ vcvtdi(result, STMP);
   } else {
     Label* deopt = compiler->AddDeoptStub(deopt_id_,
                                           ICData::kDeoptBinaryDoubleOp);
-    Register temp = locs()->temp(0).reg();
+    const Register temp = locs()->temp(0).reg();
     if (value_type->is_nullable() &&
         (value_type->ToNullableCid() == kDoubleCid)) {
       __ CompareImmediate(value, reinterpret_cast<intptr_t>(Object::null()));
       __ b(deopt, EQ);
       // It must be double now.
       __ LoadDFromOffset(result, value,
           Double::value_offset() - kHeapObjectTag);
     } else {
       Label is_smi, done;
       __ tst(value, ShifterOperand(kSmiTagMask));
@@ skipping 284 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void BinaryFloat32x4OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   switch (op_kind()) {
     case Token::kADD: __ vaddqs(result, left, right); break;
     case Token::kSUB: __ vsubqs(result, left, right); break;
     case Token::kMUL: __ vmulqs(result, left, right); break;
     case Token::kDIV: __ Vdivqs(result, left, right); break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* BinaryFloat64x2OpInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void BinaryFloat64x2OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister left0 = EvenDRegisterOf(left);
-  DRegister left1 = OddDRegisterOf(left);
+  const DRegister left0 = EvenDRegisterOf(left);
+  const DRegister left1 = OddDRegisterOf(left);
 
-  DRegister right0 = EvenDRegisterOf(right);
-  DRegister right1 = OddDRegisterOf(right);
+  const DRegister right0 = EvenDRegisterOf(right);
+  const DRegister right1 = OddDRegisterOf(right);
 
-  DRegister result0 = EvenDRegisterOf(result);
-  DRegister result1 = OddDRegisterOf(result);
+  const DRegister result0 = EvenDRegisterOf(result);
+  const DRegister result1 = OddDRegisterOf(result);
 
   switch (op_kind()) {
     case Token::kADD:
       __ vaddd(result0, left0, right0);
       __ vaddd(result1, left1, right1);
       break;
     case Token::kSUB:
       __ vsubd(result0, left0, right0);
       __ vsubd(result1, left1, right1);
       break;
@@ skipping 16 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   // Low (< Q7) Q registers are needed for the vcvtds and vmovs instructions.
   summary->set_in(0, Location::FpuRegisterLocation(Q5));
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Simd32x4ShuffleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
-  SRegister sresult0 = EvenSRegisterOf(dresult0);
-  SRegister sresult1 = OddSRegisterOf(dresult0);
-  SRegister sresult2 = EvenSRegisterOf(dresult1);
-  SRegister sresult3 = OddSRegisterOf(dresult1);
+  const QRegister value = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
+  const SRegister sresult0 = EvenSRegisterOf(dresult0);
+  const SRegister sresult1 = OddSRegisterOf(dresult0);
+  const SRegister sresult2 = EvenSRegisterOf(dresult1);
+  const SRegister sresult3 = OddSRegisterOf(dresult1);
 
-  DRegister dvalue0 = EvenDRegisterOf(value);
-  DRegister dvalue1 = OddDRegisterOf(value);
+  const DRegister dvalue0 = EvenDRegisterOf(value);
+  const DRegister dvalue1 = OddDRegisterOf(value);
 
-  DRegister dtemp0 = DTMP;
-  DRegister dtemp1 = OddDRegisterOf(QTMP);
+  const DRegister dtemp0 = DTMP;
+  const DRegister dtemp1 = OddDRegisterOf(QTMP);
 
   // For some cases the vdup instruction requires fewer
   // instructions. For arbitrary shuffles, use vtbl.
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4ShuffleX:
       __ vdup(kWord, result, dvalue0, 0);
       __ vcvtds(dresult0, sresult0);
       break;
     case MethodRecognizer::kFloat32x4ShuffleY:
@@ skipping 47 matching lines @@
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   // Low (< Q7) Q registers are needed for the vcvtds and vmovs instructions.
   summary->set_in(0, Location::FpuRegisterLocation(Q4));
   summary->set_in(1, Location::FpuRegisterLocation(Q5));
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Simd32x4ShuffleMixInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
-  SRegister sresult0 = EvenSRegisterOf(dresult0);
-  SRegister sresult1 = OddSRegisterOf(dresult0);
-  SRegister sresult2 = EvenSRegisterOf(dresult1);
-  SRegister sresult3 = OddSRegisterOf(dresult1);
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
+  const SRegister sresult0 = EvenSRegisterOf(dresult0);
+  const SRegister sresult1 = OddSRegisterOf(dresult0);
+  const SRegister sresult2 = EvenSRegisterOf(dresult1);
+  const SRegister sresult3 = OddSRegisterOf(dresult1);
 
-  DRegister dleft0 = EvenDRegisterOf(left);
-  DRegister dleft1 = OddDRegisterOf(left);
-  DRegister dright0 = EvenDRegisterOf(right);
-  DRegister dright1 = OddDRegisterOf(right);
+  const DRegister dleft0 = EvenDRegisterOf(left);
+  const DRegister dleft1 = OddDRegisterOf(left);
+  const DRegister dright0 = EvenDRegisterOf(right);
+  const DRegister dright1 = OddDRegisterOf(right);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4ShuffleMix:
     case MethodRecognizer::kInt32x4ShuffleMix:
       // TODO(zra): Investigate better instruction sequences for shuffle masks.
       SRegister left_svalues[4];
       SRegister right_svalues[4];
 
       left_svalues[0] = EvenSRegisterOf(dleft0);
       left_svalues[1] = OddSRegisterOf(dleft0);
@@ skipping 20 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::FpuRegisterLocation(Q5));
   summary->set_temp(0, Location::RequiresRegister());
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void Simd32x4GetSignMaskInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  DRegister dvalue0 = EvenDRegisterOf(value);
-  DRegister dvalue1 = OddDRegisterOf(value);
+  const QRegister value = locs()->in(0).fpu_reg();
+  const DRegister dvalue0 = EvenDRegisterOf(value);
+  const DRegister dvalue1 = OddDRegisterOf(value);
 
-  Register out = locs()->out(0).reg();
-  Register temp = locs()->temp(0).reg();
+  const Register out = locs()->out(0).reg();
+  const Register temp = locs()->temp(0).reg();
 
   // X lane.
   __ vmovrs(out, EvenSRegisterOf(dvalue0));
   __ Lsr(out, out, 31);
   // Y lane.
   __ vmovrs(temp, OddSRegisterOf(dvalue0));
   __ Lsr(temp, temp, 31);
   __ orr(out, out, ShifterOperand(temp, LSL, 1));
   // Z lane.
   __ vmovrs(temp, EvenSRegisterOf(dvalue1));
@@ skipping 18 matching lines @@
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_in(2, Location::RequiresFpuRegister());
   summary->set_in(3, Location::RequiresFpuRegister());
   // Low (< 7) Q registers are needed for the vcvtsd instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Float32x4ConstructorInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q0 = locs()->in(0).fpu_reg();
-  QRegister q1 = locs()->in(1).fpu_reg();
-  QRegister q2 = locs()->in(2).fpu_reg();
-  QRegister q3 = locs()->in(3).fpu_reg();
-  QRegister r = locs()->out(0).fpu_reg();
+  const QRegister q0 = locs()->in(0).fpu_reg();
+  const QRegister q1 = locs()->in(1).fpu_reg();
+  const QRegister q2 = locs()->in(2).fpu_reg();
+  const QRegister q3 = locs()->in(3).fpu_reg();
+  const QRegister r = locs()->out(0).fpu_reg();
 
-  DRegister dr0 = EvenDRegisterOf(r);
-  DRegister dr1 = OddDRegisterOf(r);
+  const DRegister dr0 = EvenDRegisterOf(r);
+  const DRegister dr1 = OddDRegisterOf(r);
 
   __ vcvtsd(EvenSRegisterOf(dr0), EvenDRegisterOf(q0));
   __ vcvtsd(OddSRegisterOf(dr0), EvenDRegisterOf(q1));
   __ vcvtsd(EvenSRegisterOf(dr1), EvenDRegisterOf(q2));
   __ vcvtsd(OddSRegisterOf(dr1), EvenDRegisterOf(q3));
 }
 
 
 LocationSummary* Float32x4ZeroInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 0;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ZeroInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q = locs()->out(0).fpu_reg();
+  const QRegister q = locs()->out(0).fpu_reg();
   __ veorq(q, q, q);
 }
 
 
 LocationSummary* Float32x4SplatInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4SplatInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dvalue0 = EvenDRegisterOf(value);
+  const DRegister dvalue0 = EvenDRegisterOf(value);
 
   // Convert to Float32.
   __ vcvtsd(STMP, dvalue0);
 
   // Splat across all lanes.
   __ vdup(kWord, result, DTMP, 0);
 }
 
 
 LocationSummary* Float32x4ComparisonInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ComparisonInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4Equal:
       __ vceqqs(result, left, right);
       break;
     case MethodRecognizer::kFloat32x4NotEqual:
       __ vceqqs(result, left, right);
       // Invert the result.
       __ vmvnq(result, result);
       break;
@@ skipping 21 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4MinMaxInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4Min:
       __ vminqs(result, left, right);
       break;
     case MethodRecognizer::kFloat32x4Max:
       __ vmaxqs(result, left, right);
       break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* Float32x4SqrtInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 1;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   summary->set_temp(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4SqrtInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
-  QRegister temp = locs()->temp(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
+  const QRegister temp = locs()->temp(0).fpu_reg();
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4Sqrt:
       __ Vsqrtqs(result, left, temp);
       break;
     case MethodRecognizer::kFloat32x4Reciprocal:
       __ Vreciprocalqs(result, left);
       break;
     case MethodRecognizer::kFloat32x4ReciprocalSqrt:
       __ VreciprocalSqrtqs(result, left);
       break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* Float32x4ScaleInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ScaleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4Scale:
       __ vcvtsd(STMP, EvenDRegisterOf(left));
       __ vdup(kWord, result, DTMP, 0);
       __ vmulqs(result, result, right);
       break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* Float32x4ZeroArgInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ZeroArgInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4Negate:
       __ vnegqs(result, left);
       break;
     case MethodRecognizer::kFloat32x4Absolute:
       __ vabsqs(result, left);
       break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* Float32x4ClampInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 3;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_in(2, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ClampInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister lower = locs()->in(1).fpu_reg();
-  QRegister upper = locs()->in(2).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister lower = locs()->in(1).fpu_reg();
+  const QRegister upper = locs()->in(2).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
   __ vminqs(result, left, upper);
   __ vmaxqs(result, result, lower);
 }
 
 
 LocationSummary* Float32x4WithInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   // Low (< 7) Q registers are needed for the vmovs instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Float32x4WithInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister replacement = locs()->in(0).fpu_reg();
-  QRegister value = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister replacement = locs()->in(0).fpu_reg();
+  const QRegister value = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
-  SRegister sresult0 = EvenSRegisterOf(dresult0);
-  SRegister sresult1 = OddSRegisterOf(dresult0);
-  SRegister sresult2 = EvenSRegisterOf(dresult1);
-  SRegister sresult3 = OddSRegisterOf(dresult1);
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
+  const SRegister sresult0 = EvenSRegisterOf(dresult0);
+  const SRegister sresult1 = OddSRegisterOf(dresult0);
+  const SRegister sresult2 = EvenSRegisterOf(dresult1);
+  const SRegister sresult3 = OddSRegisterOf(dresult1);
 
   __ vcvtsd(STMP, EvenDRegisterOf(replacement));
   if (result != value) {
     __ vmovq(result, value);
   }
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4WithX:
       __ vmovs(sresult0, STMP);
       break;
@@ skipping 16 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float32x4ToInt32x4Instr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   if (value != result) {
     __ vmovq(result, value);
   }
 }
 
 
 LocationSummary* Simd64x2ShuffleInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Simd64x2ShuffleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
 
-  DRegister dvalue0 = EvenDRegisterOf(value);
-  DRegister dvalue1 = OddDRegisterOf(value);
+  const DRegister dvalue0 = EvenDRegisterOf(value);
+  const DRegister dvalue1 = OddDRegisterOf(value);
 
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult0 = EvenDRegisterOf(result);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat64x2GetX:
       __ vmovd(dresult0, dvalue0);
       break;
     case MethodRecognizer::kFloat64x2GetY:
       __ vmovd(dresult0, dvalue1);
       break;
     default: UNREACHABLE();
   }
 }
 
 
 LocationSummary* Float64x2ZeroInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 0;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float64x2ZeroInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q = locs()->out(0).fpu_reg();
+  const QRegister q = locs()->out(0).fpu_reg();
   __ veorq(q, q, q);
 }
 
 
 LocationSummary* Float64x2SplatInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float64x2SplatInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
 
-  DRegister dvalue = EvenDRegisterOf(value);
+  const DRegister dvalue = EvenDRegisterOf(value);
 
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
 
   // Splat across all lanes.
   __ vmovd(dresult0, dvalue);
   __ vmovd(dresult1, dvalue);
 }
 
 
 LocationSummary* Float64x2ConstructorInstr::MakeLocationSummary(
     bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Float64x2ConstructorInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q0 = locs()->in(0).fpu_reg();
-  QRegister q1 = locs()->in(1).fpu_reg();
-  QRegister r = locs()->out(0).fpu_reg();
+  const QRegister q0 = locs()->in(0).fpu_reg();
+  const QRegister q1 = locs()->in(1).fpu_reg();
+  const QRegister r = locs()->out(0).fpu_reg();
 
-  DRegister d0 = EvenDRegisterOf(q0);
-  DRegister d1 = EvenDRegisterOf(q1);
+  const DRegister d0 = EvenDRegisterOf(q0);
+  const DRegister d1 = EvenDRegisterOf(q1);
 
-  DRegister dr0 = EvenDRegisterOf(r);
-  DRegister dr1 = OddDRegisterOf(r);
+  const DRegister dr0 = EvenDRegisterOf(r);
+  const DRegister dr1 = OddDRegisterOf(r);
 
   __ vmovd(dr0, d0);
   __ vmovd(dr1, d1);
 }
 
 
 LocationSummary* Float64x2ToFloat32x4Instr::MakeLocationSummary(
     bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   // Low (< 7) Q registers are needed for the vcvtsd instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Float64x2ToFloat32x4Instr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q = locs()->in(0).fpu_reg();
-  QRegister r = locs()->out(0).fpu_reg();
+  const QRegister q = locs()->in(0).fpu_reg();
+  const QRegister r = locs()->out(0).fpu_reg();
 
-  DRegister dq0 = EvenDRegisterOf(q);
-  DRegister dq1 = OddDRegisterOf(q);
+  const DRegister dq0 = EvenDRegisterOf(q);
+  const DRegister dq1 = OddDRegisterOf(q);
 
-  DRegister dr0 = EvenDRegisterOf(r);
+  const DRegister dr0 = EvenDRegisterOf(r);
 
   // Zero register.
   __ veorq(r, r, r);
   // Set X lane.
   __ vcvtsd(EvenSRegisterOf(dr0), dq0);
   // Set Y lane.
   __ vcvtsd(OddSRegisterOf(dr0), dq1);
 }
 
 
 LocationSummary* Float32x4ToFloat64x2Instr::MakeLocationSummary(
     bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   // Low (< 7) Q registers are needed for the vcvtsd instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Float32x4ToFloat64x2Instr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q = locs()->in(0).fpu_reg();
-  QRegister r = locs()->out(0).fpu_reg();
+  const QRegister q = locs()->in(0).fpu_reg();
+  const QRegister r = locs()->out(0).fpu_reg();
 
-  DRegister dq0 = EvenDRegisterOf(q);
+  const DRegister dq0 = EvenDRegisterOf(q);
 
-  DRegister dr0 = EvenDRegisterOf(r);
-  DRegister dr1 = OddDRegisterOf(r);
+  const DRegister dr0 = EvenDRegisterOf(r);
+  const DRegister dr1 = OddDRegisterOf(r);
 
   // Set X.
   __ vcvtds(dr0, EvenSRegisterOf(dq0));
   // Set Y.
   __ vcvtds(dr1, OddSRegisterOf(dq0));
 }
 
 
 LocationSummary* Float64x2ZeroArgInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
 
   if (representation() == kTagged) {
     ASSERT(op_kind() == MethodRecognizer::kFloat64x2GetSignMask);
     // Grabbing the S components means we need a low (< 7) Q.
     summary->set_in(0, Location::FpuRegisterLocation(Q6));
     summary->set_out(0, Location::RequiresRegister());
     summary->AddTemp(Location::RequiresRegister());
   } else {
     summary->set_in(0, Location::RequiresFpuRegister());
     summary->set_out(0, Location::RequiresFpuRegister());
   }
   return summary;
 }
 
 
 void Float64x2ZeroArgInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister q = locs()->in(0).fpu_reg();
+  const QRegister q = locs()->in(0).fpu_reg();
 
   if ((op_kind() == MethodRecognizer::kFloat64x2GetSignMask)) {
-    DRegister dvalue0 = EvenDRegisterOf(q);
-    DRegister dvalue1 = OddDRegisterOf(q);
+    const DRegister dvalue0 = EvenDRegisterOf(q);
+    const DRegister dvalue1 = OddDRegisterOf(q);
 
-    Register out = locs()->out(0).reg();
-    Register temp = locs()->temp(0).reg();
+    const Register out = locs()->out(0).reg();
+    const Register temp = locs()->temp(0).reg();
 
     // Upper 32-bits of X lane.
     __ vmovrs(out, OddSRegisterOf(dvalue0));
     __ Lsr(out, out, 31);
     // Upper 32-bits of Y lane.
     __ vmovrs(temp, OddSRegisterOf(dvalue1));
     __ Lsr(temp, temp, 31);
     __ orr(out, out, ShifterOperand(temp, LSL, 1));
     // Tag.
     __ SmiTag(out);
     return;
   }
   ASSERT(representation() == kUnboxedFloat64x2);
-  QRegister r = locs()->out(0).fpu_reg();
+  const QRegister r = locs()->out(0).fpu_reg();
 
-  DRegister dvalue0 = EvenDRegisterOf(q);
-  DRegister dvalue1 = OddDRegisterOf(q);
-  DRegister dresult0 = EvenDRegisterOf(r);
-  DRegister dresult1 = OddDRegisterOf(r);
+  const DRegister dvalue0 = EvenDRegisterOf(q);
+  const DRegister dvalue1 = OddDRegisterOf(q);
+  const DRegister dresult0 = EvenDRegisterOf(r);
+  const DRegister dresult1 = OddDRegisterOf(r);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat64x2Negate:
       __ vnegd(dresult0, dvalue0);
       __ vnegd(dresult1, dvalue1);
       break;
     case MethodRecognizer::kFloat64x2Abs:
       __ vabsd(dresult0, dvalue0);
       __ vabsd(dresult1, dvalue1);
       break;
@@ skipping 12 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::SameAsFirstInput());
   return summary;
 }
 
 
 void Float64x2OneArgInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  DRegister left0 = EvenDRegisterOf(left);
-  DRegister left1 = OddDRegisterOf(left);
-  QRegister right = locs()->in(1).fpu_reg();
-  DRegister right0 = EvenDRegisterOf(right);
-  DRegister right1 = OddDRegisterOf(right);
-  QRegister out = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const DRegister left0 = EvenDRegisterOf(left);
+  const DRegister left1 = OddDRegisterOf(left);
+  const QRegister right = locs()->in(1).fpu_reg();
+  const DRegister right0 = EvenDRegisterOf(right);
+  const DRegister right1 = OddDRegisterOf(right);
+  const QRegister out = locs()->out(0).fpu_reg();
   ASSERT(left == out);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat64x2Scale:
       __ vmuld(left0, left0, right0);
       __ vmuld(left1, left1, right0);
       break;
     case MethodRecognizer::kFloat64x2WithX:
       __ vmovd(left0, right0);
       break;
@@ skipping 50 matching lines @@
   summary->set_in(2, Location::RequiresRegister());
   summary->set_in(3, Location::RequiresRegister());
   summary->set_temp(0, Location::RequiresRegister());
   // Low (< 7) Q register needed for the vmovsr instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Int32x4BoolConstructorInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register v0 = locs()->in(0).reg();
-  Register v1 = locs()->in(1).reg();
-  Register v2 = locs()->in(2).reg();
-  Register v3 = locs()->in(3).reg();
-  Register temp = locs()->temp(0).reg();
-  QRegister result = locs()->out(0).fpu_reg();
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
-  SRegister sresult0 = EvenSRegisterOf(dresult0);
-  SRegister sresult1 = OddSRegisterOf(dresult0);
-  SRegister sresult2 = EvenSRegisterOf(dresult1);
-  SRegister sresult3 = OddSRegisterOf(dresult1);
+  const Register v0 = locs()->in(0).reg();
+  const Register v1 = locs()->in(1).reg();
+  const Register v2 = locs()->in(2).reg();
+  const Register v3 = locs()->in(3).reg();
+  const Register temp = locs()->temp(0).reg();
+  const QRegister result = locs()->out(0).fpu_reg();
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
+  const SRegister sresult0 = EvenSRegisterOf(dresult0);
+  const SRegister sresult1 = OddSRegisterOf(dresult0);
+  const SRegister sresult2 = EvenSRegisterOf(dresult1);
+  const SRegister sresult3 = OddSRegisterOf(dresult1);
 
   __ veorq(result, result, result);
   __ LoadImmediate(temp, 0xffffffff);
 
   __ CompareObject(v0, Bool::True());
   __ vmovsr(sresult0, temp, EQ);
 
   __ CompareObject(v1, Bool::True());
   __ vmovsr(sresult1, temp, EQ);
 
@@ skipping 11 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   // Low (< 7) Q registers are needed for the vmovrs instruction.
   summary->set_in(0, Location::FpuRegisterLocation(Q6));
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void Int32x4GetFlagInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  Register result = locs()->out(0).reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const Register result = locs()->out(0).reg();
 
-  DRegister dvalue0 = EvenDRegisterOf(value);
-  DRegister dvalue1 = OddDRegisterOf(value);
-  SRegister svalue0 = EvenSRegisterOf(dvalue0);
-  SRegister svalue1 = OddSRegisterOf(dvalue0);
-  SRegister svalue2 = EvenSRegisterOf(dvalue1);
-  SRegister svalue3 = OddSRegisterOf(dvalue1);
+  const DRegister dvalue0 = EvenDRegisterOf(value);
+  const DRegister dvalue1 = OddDRegisterOf(value);
+  const SRegister svalue0 = EvenSRegisterOf(dvalue0);
+  const SRegister svalue1 = OddSRegisterOf(dvalue0);
+  const SRegister svalue2 = EvenSRegisterOf(dvalue1);
+  const SRegister svalue3 = OddSRegisterOf(dvalue1);
 
   switch (op_kind()) {
     case MethodRecognizer::kInt32x4GetFlagX:
       __ vmovrs(result, svalue0);
       break;
     case MethodRecognizer::kInt32x4GetFlagY:
       __ vmovrs(result, svalue1);
       break;
     case MethodRecognizer::kInt32x4GetFlagZ:
       __ vmovrs(result, svalue2);
@@ skipping 18 matching lines @@
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_in(2, Location::RequiresFpuRegister());
   summary->set_temp(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Int32x4SelectInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister mask = locs()->in(0).fpu_reg();
-  QRegister trueValue = locs()->in(1).fpu_reg();
-  QRegister falseValue = locs()->in(2).fpu_reg();
-  QRegister out = locs()->out(0).fpu_reg();
-  QRegister temp = locs()->temp(0).fpu_reg();
+  const QRegister mask = locs()->in(0).fpu_reg();
+  const QRegister trueValue = locs()->in(1).fpu_reg();
+  const QRegister falseValue = locs()->in(2).fpu_reg();
+  const QRegister out = locs()->out(0).fpu_reg();
+  const QRegister temp = locs()->temp(0).fpu_reg();
 
   // Copy mask.
   __ vmovq(temp, mask);
   // Invert it.
   __ vmvnq(temp, temp);
   // mask = mask & trueValue.
   __ vandq(mask, mask, trueValue);
   // temp = temp & falseValue.
   __ vandq(temp, temp, falseValue);
   // out = mask | temp.
   __ vorrq(out, mask, temp);
 }
 
 
 LocationSummary* Int32x4SetFlagInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresRegister());
   // Low (< 7) Q register needed for the vmovsr instruction.
   summary->set_out(0, Location::FpuRegisterLocation(Q6));
   return summary;
 }
 
 
 void Int32x4SetFlagInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister mask = locs()->in(0).fpu_reg();
-  Register flag = locs()->in(1).reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister mask = locs()->in(0).fpu_reg();
+  const Register flag = locs()->in(1).reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
-  DRegister dresult0 = EvenDRegisterOf(result);
-  DRegister dresult1 = OddDRegisterOf(result);
-  SRegister sresult0 = EvenSRegisterOf(dresult0);
-  SRegister sresult1 = OddSRegisterOf(dresult0);
-  SRegister sresult2 = EvenSRegisterOf(dresult1);
-  SRegister sresult3 = OddSRegisterOf(dresult1);
+  const DRegister dresult0 = EvenDRegisterOf(result);
+  const DRegister dresult1 = OddDRegisterOf(result);
+  const SRegister sresult0 = EvenSRegisterOf(dresult0);
+  const SRegister sresult1 = OddSRegisterOf(dresult0);
+  const SRegister sresult2 = EvenSRegisterOf(dresult1);
+  const SRegister sresult3 = OddSRegisterOf(dresult1);
 
   if (result != mask) {
     __ vmovq(result, mask);
   }
 
   __ CompareObject(flag, Bool::True());
   __ LoadImmediate(TMP, 0xffffffff, EQ);
   __ LoadImmediate(TMP, 0, NE);
   switch (op_kind()) {
     case MethodRecognizer::kInt32x4WithFlagX:
@@ skipping 18 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void Int32x4ToFloat32x4Instr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
 
   if (value != result) {
     __ vmovq(result, value);
   }
 }
 
 
 LocationSummary* BinaryInt32x4OpInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void BinaryInt32x4OpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister result = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister result = locs()->out(0).fpu_reg();
   switch (op_kind()) {
     case Token::kBIT_AND: {
       __ vandq(result, left, right);
       break;
     }
     case Token::kBIT_OR: {
       __ vorrq(result, left, right);
       break;
     }
     case Token::kBIT_XOR: {
@@ skipping 34 matching lines @@
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void MathUnaryInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   if (kind() == MathUnaryInstr::kSqrt) {
-    DRegister val = EvenDRegisterOf(locs()->in(0).fpu_reg());
-    DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+    const DRegister val = EvenDRegisterOf(locs()->in(0).fpu_reg());
+    const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
     __ vsqrtd(result, val);
   } else if (kind() == MathUnaryInstr::kDoubleSquare) {
-    DRegister val = EvenDRegisterOf(locs()->in(0).fpu_reg());
-    DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+    const DRegister val = EvenDRegisterOf(locs()->in(0).fpu_reg());
+    const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
     __ vmuld(result, val, val);
   } else {
     ASSERT((kind() == MathUnaryInstr::kSin) ||
            (kind() == MathUnaryInstr::kCos));
     if (TargetCPUFeatures::hardfp_supported()) {
       __ CallRuntime(TargetFunction(), InputCount());
       } else {
       // If we aren't doing "hardfp", then we have to move the double arguments
       // to the integer registers, and take the results from the integer
       // registers.
@@ skipping 32 matching lines @@
   return summary;
 }
 
 
 void MathMinMaxInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT((op_kind() == MethodRecognizer::kMathMin) ||
          (op_kind() == MethodRecognizer::kMathMax));
   const intptr_t is_min = (op_kind() == MethodRecognizer::kMathMin);
   if (result_cid() == kDoubleCid) {
     Label done, returns_nan, are_equal;
-    DRegister left = EvenDRegisterOf(locs()->in(0).fpu_reg());
-    DRegister right = EvenDRegisterOf(locs()->in(1).fpu_reg());
-    DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
-    Register temp = locs()->temp(0).reg();
+    const DRegister left = EvenDRegisterOf(locs()->in(0).fpu_reg());
+    const DRegister right = EvenDRegisterOf(locs()->in(1).fpu_reg());
+    const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+    const Register temp = locs()->temp(0).reg();
     __ vcmpd(left, right);
     __ vmstat();
     __ b(&returns_nan, VS);
     __ b(&are_equal, EQ);
     const Condition neg_double_condition =
         is_min ? TokenKindToDoubleCondition(Token::kGTE)
                : TokenKindToDoubleCondition(Token::kLTE);
     ASSERT(left == result);
     __ vmovd(result, right, neg_double_condition);
     __ b(&done);
@@ skipping 16 matching lines @@
       __ vmovd(result, right, GE);
     } else {
       __ vmovd(result, right, LT);
       ASSERT(left == result);
     }
     __ Bind(&done);
     return;
   }
 
   ASSERT(result_cid() == kSmiCid);
-  Register left = locs()->in(0).reg();
-  Register right = locs()->in(1).reg();
-  Register result = locs()->out(0).reg();
+  const Register left = locs()->in(0).reg();
+  const Register right = locs()->in(1).reg();
+  const Register result = locs()->out(0).reg();
   __ cmp(left, ShifterOperand(right));
   ASSERT(result == left);
   if (is_min) {
     __ mov(result, ShifterOperand(right), GT);
   } else {
     __ mov(result, ShifterOperand(right), LT);
   }
 }
 
 
 LocationSummary* UnarySmiOpInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresRegister());
   // We make use of 3-operand instructions by not requiring result register
   // to be identical to first input register as on Intel.
   summary->set_out(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void UnarySmiOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register value = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
   switch (op_kind()) {
     case Token::kNEGATE: {
       Label* deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptUnaryOp);
       __ rsbs(result, value, ShifterOperand(0));
       __ b(deopt, VS);
       break;
     }
     case Token::kBIT_NOT:
       __ mvn(result, ShifterOperand(value));
       // Remove inverted smi-tag.
@@ skipping 10 matching lines @@
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void UnaryDoubleOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
-  DRegister value = EvenDRegisterOf(locs()->in(0).fpu_reg());
+  const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+  const DRegister value = EvenDRegisterOf(locs()->in(0).fpu_reg());
   __ vnegd(result, value);
 }
 
 
 LocationSummary* SmiToDoubleInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* result =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   result->set_in(0, Location::WritableRegister());
   result->set_out(0, Location::RequiresFpuRegister());
   return result;
 }
 
 
 void SmiToDoubleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
-  DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+  const Register value = locs()->in(0).reg();
+  const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
   __ SmiUntag(value);
   __ vmovsr(STMP, value);
   __ vcvtdi(result, STMP);
 }
 
 
 LocationSummary* DoubleToIntegerInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* result =
@@ skipping 92 matching lines @@
   LocationSummary* result =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   // Low (<= Q7) Q registers are needed for the conversion instructions.
   result->set_in(0, Location::RequiresFpuRegister());
   result->set_out(0, Location::FpuRegisterLocation(Q7));
   return result;
 }
 
 
 void DoubleToFloatInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  DRegister value = EvenDRegisterOf(locs()->in(0).fpu_reg());
-  SRegister result = EvenSRegisterOf(EvenDRegisterOf(locs()->out(0).fpu_reg()));
+  const DRegister value = EvenDRegisterOf(locs()->in(0).fpu_reg());
+  const SRegister result =
+      EvenSRegisterOf(EvenDRegisterOf(locs()->out(0).fpu_reg()));
   __ vcvtsd(result, value);
 }
 
 
 LocationSummary* FloatToDoubleInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* result =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   // Low (<= Q7) Q registers are needed for the conversion instructions.
   result->set_in(0, Location::FpuRegisterLocation(Q7));
   result->set_out(0, Location::RequiresFpuRegister());
   return result;
 }
 
 
 void FloatToDoubleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  SRegister value = EvenSRegisterOf(EvenDRegisterOf(locs()->in(0).fpu_reg()));
-  DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
+  const SRegister value =
+      EvenSRegisterOf(EvenDRegisterOf(locs()->in(0).fpu_reg()));
+  const DRegister result = EvenDRegisterOf(locs()->out(0).fpu_reg());
   __ vcvtds(result, value);
 }
 
 
 LocationSummary* InvokeMathCFunctionInstr::MakeLocationSummary(bool opt) const {
   ASSERT((InputCount() == 1) || (InputCount() == 2));
   const intptr_t kNumTemps = 0;
   LocationSummary* result =
       new LocationSummary(InputCount(), kNumTemps, LocationSummary::kCall);
   result->set_in(0, Location::FpuRegisterLocation(Q0));
@@ skipping 204 matching lines @@
   }
   return summary;
 }
 
 
 void ExtractNthOutputInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT(locs()->in(0).IsPairLocation());
   PairLocation* pair = locs()->in(0).AsPairLocation();
   Location in_loc = pair->At(index());
   if (representation() == kUnboxedDouble) {
-    QRegister out = locs()->out(0).fpu_reg();
-    QRegister in = in_loc.fpu_reg();
+    const QRegister out = locs()->out(0).fpu_reg();
+    const QRegister in = in_loc.fpu_reg();
     __ vmovq(out, in);
   } else {
     ASSERT(representation() == kTagged);
-    Register out = locs()->out(0).reg();
-    Register in = in_loc.reg();
+    const Register out = locs()->out(0).reg();
+    const Register in = in_loc.reg();
     __ mov(out, ShifterOperand(in));
   }
 }
 
 
 LocationSummary* MergedMathInstr::MakeLocationSummary(bool opt) const {
   if (kind() == MergedMathInstr::kTruncDivMod) {
     const intptr_t kNumInputs = 2;
     const intptr_t kNumTemps = 2;
     LocationSummary* summary =
@@ skipping 11 matching lines @@
   return NULL;
 }
 
 
 void MergedMathInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   Label* deopt = NULL;
   if (CanDeoptimize()) {
     deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptBinarySmiOp);
   }
   if (kind() == MergedMathInstr::kTruncDivMod) {
-    Register left = locs()->in(0).reg();
-    Register right = locs()->in(1).reg();
+    const Register left = locs()->in(0).reg();
+    const Register right = locs()->in(1).reg();
     ASSERT(locs()->out(0).IsPairLocation());
     PairLocation* pair = locs()->out(0).AsPairLocation();
-    Register result_div = pair->At(0).reg();
-    Register result_mod = pair->At(1).reg();
+    const Register result_div = pair->At(0).reg();
+    const Register result_mod = pair->At(1).reg();
     Range* right_range = InputAt(1)->definition()->range();
     if ((right_range == NULL) || right_range->Overlaps(0, 0)) {
       // Handle divide by zero in runtime.
       __ cmp(right, ShifterOperand(0));
       __ b(deopt, EQ);
     }
-    Register temp = locs()->temp(0).reg();
-    DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
+    const Register temp = locs()->temp(0).reg();
+    const DRegister dtemp = EvenDRegisterOf(locs()->temp(1).fpu_reg());
 
     __ Asr(temp, left, kSmiTagSize);  // SmiUntag left into temp.
     __ Asr(IP, right, kSmiTagSize);  // SmiUntag right into IP.
 
     __ IntegerDivide(result_div, temp, IP, dtemp, DTMP);
 
     // Check the corner case of dividing the 'MIN_SMI' with -1, in which
     // case we cannot tag the result.
     __ CompareImmediate(result_div, 0x40000000);
     __ b(deopt, EQ);
@@ skipping 105 matching lines @@
   if (IsNullCheck()) {
     Label* deopt = compiler->AddDeoptStub(deopt_id(), deopt_reason);
     __ CompareImmediate(locs()->in(0).reg(),
                         reinterpret_cast<intptr_t>(Object::null()));
     __ b(deopt, EQ);
     return;
   }
 
   ASSERT((unary_checks().GetReceiverClassIdAt(0) != kSmiCid) ||
          (unary_checks().NumberOfChecks() > 1));
-  Register value = locs()->in(0).reg();
-  Register temp = locs()->temp(0).reg();
+  const Register value = locs()->in(0).reg();
+  const Register temp = locs()->temp(0).reg();
   Label* deopt = compiler->AddDeoptStub(deopt_id(), deopt_reason);
   Label is_ok;
   intptr_t cix = 0;
   if (unary_checks().GetReceiverClassIdAt(cix) == kSmiCid) {
     __ tst(value, ShifterOperand(kSmiTagMask));
     __ b(&is_ok, EQ);
     cix++;  // Skip first check.
   } else {
     __ tst(value, ShifterOperand(kSmiTagMask));
     __ b(deopt, EQ);
@@ skipping 17 matching lines @@
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresRegister());
   return summary;
 }
 
 
 void CheckSmiInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
+  const Register value = locs()->in(0).reg();
   Label* deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptCheckSmi);
   __ tst(value, ShifterOperand(kSmiTagMask));
   __ b(deopt, NE);
 }
 
 
 LocationSummary* CheckArrayBoundInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps = 0;
   LocationSummary* locs =
@@ skipping 15 matching lines @@
     ASSERT((Smi::Cast(length_loc.constant()).Value() <=
             Smi::Cast(index_loc.constant()).Value()) ||
            (Smi::Cast(index_loc.constant()).Value() < 0));
     // Unconditionally deoptimize for constant bounds checks because they
     // only occur only when index is out-of-bounds.
     __ b(deopt);
     return;
   }
 
   if (index_loc.IsConstant()) {
-    Register length = length_loc.reg();
+    const Register length = length_loc.reg();
     const Smi& index = Smi::Cast(index_loc.constant());
     __ CompareImmediate(length, reinterpret_cast<int32_t>(index.raw()));
     __ b(deopt, LS);
   } else if (length_loc.IsConstant()) {
     const Smi& length = Smi::Cast(length_loc.constant());
-    Register index = index_loc.reg();
+    const Register index = index_loc.reg();
     __ CompareImmediate(index, reinterpret_cast<int32_t>(length.raw()));
     __ b(deopt, CS);
   } else {
-    Register length = length_loc.reg();
-    Register index = index_loc.reg();
+    const Register length = length_loc.reg();
+    const Register index = index_loc.reg();
     __ cmp(index, ShifterOperand(length));
     __ b(deopt, CS);
   }
 }
 
 
 static void EmitJavascriptIntOverflowCheck(FlowGraphCompiler* compiler,
                                            Label* overflow,
                                            QRegister result,
                                            Register tmp_hi, Register tmp_lo) {
@@ skipping 38 matching lines @@
   const intptr_t value_cid = value()->Type()->ToCid();
   const Register value = locs()->in(0).reg();
   const QRegister result = locs()->out(0).fpu_reg();
 
   __ Comment("UnboxIntegerInstr");
   __ veorq(result, result, result);
   if (value_cid == kMintCid) {
     __ LoadDFromOffset(EvenDRegisterOf(result), value,
                        Mint::value_offset() - kHeapObjectTag);
   } else if (value_cid == kSmiCid) {
-    Register temp = locs()->temp(0).reg();
+    const Register temp = locs()->temp(0).reg();
     __ SmiUntag(value);
     // Sign extend value into temp.
     __ Asr(temp, value, 31);
     __ vmovdrr(EvenDRegisterOf(result), value, temp);
   } else {
-    Register temp = locs()->temp(0).reg();
+    const Register temp = locs()->temp(0).reg();
     Label* deopt = compiler->AddDeoptStub(deopt_id_,
                                           ICData::kDeoptUnboxInteger);
     Label is_smi, done;
     __ tst(value, ShifterOperand(kSmiTagMask));
     __ b(&is_smi, EQ);
     __ CompareClassId(value, kMintCid, temp);
     __ b(deopt, NE);
 
     // It's a Mint.
     __ LoadDFromOffset(EvenDRegisterOf(result), value,
@@ skipping 56 matching lines @@
 
  private:
   BoxIntegerInstr* instruction_;
 };
 
 
 void BoxIntegerInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   BoxIntegerSlowPath* slow_path = new BoxIntegerSlowPath(this);
   compiler->AddSlowPathCode(slow_path);
 
-  Register out_reg = locs()->out(0).reg();
-  QRegister value = locs()->in(0).fpu_reg();
-  DRegister dvalue0 = EvenDRegisterOf(value);
-  Register lo = locs()->temp(0).reg();
-  Register hi = locs()->temp(1).reg();
+  const Register out_reg = locs()->out(0).reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const DRegister dvalue0 = EvenDRegisterOf(value);
+  const Register lo = locs()->temp(0).reg();
+  const Register hi = locs()->temp(1).reg();
 
   // Unboxed operations produce smis or mint-sized values.
   // Check if value fits into a smi.
   __ Comment("BoxIntegerInstr");
   Label not_smi, done, maybe_pos_smi, maybe_neg_smi, is_smi;
   __ vmovrrd(lo, hi, dvalue0);
   __ CompareImmediate(hi, 0);
   __ b(&maybe_pos_smi, EQ);
 
   __ CompareImmediate(hi, -1);
@@ skipping 46 matching lines @@
     // Need another temp for checking for overflow.
     summary->AddTemp(Location::RequiresFpuRegister());
     summary->AddTemp(Location::FpuRegisterLocation(Q7));
   }
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void BinaryMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister left = locs()->in(0).fpu_reg();
-  QRegister right = locs()->in(1).fpu_reg();
-  QRegister out = locs()->out(0).fpu_reg();
+  const QRegister left = locs()->in(0).fpu_reg();
+  const QRegister right = locs()->in(1).fpu_reg();
+  const QRegister out = locs()->out(0).fpu_reg();
 
   Label* deopt = NULL;
   if (FLAG_throw_on_javascript_int_overflow) {
     deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptBinaryMintOp);
   }
   switch (op_kind()) {
     case Token::kBIT_AND: __ vandq(out, left, right); break;
     case Token::kBIT_OR: __ vorrq(out, left, right); break;
     case Token::kBIT_XOR: __ veorq(out, left, right); break;
     case Token::kADD:
     case Token::kSUB: {
       const intptr_t tmpidx = FLAG_throw_on_javascript_int_overflow ? 2 : 0;
-      QRegister tmp = locs()->temp(tmpidx).fpu_reg();
-      QRegister ro = locs()->temp(tmpidx + 1).fpu_reg();
+      const QRegister tmp = locs()->temp(tmpidx).fpu_reg();
+      const QRegister ro = locs()->temp(tmpidx + 1).fpu_reg();
       ASSERT(ro == Q7);
       if (!FLAG_throw_on_javascript_int_overflow) {
         deopt  = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptBinaryMintOp);
       }
       if (op_kind() == Token::kADD) {
         __ vaddqi(kWordPair, out, left, right);
       } else {
         ASSERT(op_kind() == Token::kSUB);
         __ vsubqi(kWordPair, out, left, right);
       }
       __ veorq(ro, out, left);
       __ veorq(tmp, left, right);
       __ vandq(ro, tmp, ro);
       __ vmovrs(TMP, OddSRegisterOf(EvenDRegisterOf(ro)));
       // If TMP < 0, there was overflow.
       __ cmp(TMP, ShifterOperand(0));
       __ b(deopt, LT);
       break;
     }
     default: UNREACHABLE(); break;
   }
   if (FLAG_throw_on_javascript_int_overflow) {
-    Register tmp1 = locs()->temp(0).reg();
-    Register tmp2 = locs()->temp(1).reg();
+    const Register tmp1 = locs()->temp(0).reg();
+    const Register tmp2 = locs()->temp(1).reg();
     EmitJavascriptIntOverflowCheck(compiler, deopt, out, tmp1, tmp2);
   }
 }
 
 
 LocationSummary* ShiftMintOpInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 2;
   const intptr_t kNumTemps =
       FLAG_throw_on_javascript_int_overflow ? 2 : 1;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_in(1, Location::WritableRegister());
   summary->set_temp(0, Location::FpuRegisterLocation(Q7));
   if (FLAG_throw_on_javascript_int_overflow) {
     summary->set_temp(1, Location::RequiresRegister());
   }
   summary->set_out(0, Location::RequiresFpuRegister());
   return summary;
 }
 
 
 void ShiftMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  QRegister value = locs()->in(0).fpu_reg();
-  Register shift = locs()->in(1).reg();
-  QRegister temp = locs()->temp(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const Register shift = locs()->in(1).reg();
+  const QRegister temp = locs()->temp(0).fpu_reg();
   ASSERT(temp == Q7);
-  QRegister out = locs()->out(0).fpu_reg();
-  DRegister dtemp0 = EvenDRegisterOf(temp);
-  SRegister stemp0 = EvenSRegisterOf(dtemp0);
-  SRegister stemp1 = OddSRegisterOf(dtemp0);
+  const QRegister out = locs()->out(0).fpu_reg();
+  const DRegister dtemp0 = EvenDRegisterOf(temp);
+  const SRegister stemp0 = EvenSRegisterOf(dtemp0);
+  const SRegister stemp1 = OddSRegisterOf(dtemp0);
 
   Label* deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptShiftMintOp);
   Label done;
 
   __ CompareImmediate(shift, 0);
   __ vmovq(out, value);
   __ b(&done, EQ);
   __ SmiUntag(shift);
 
   // vshlq takes the shift value from low byte. Deopt if shift is
@@ skipping 30 matching lines @@
       __ b(deopt, NE);
       break;
     }
     default:
       UNREACHABLE();
       break;
   }
 
   __ Bind(&done);
   if (FLAG_throw_on_javascript_int_overflow) {
-    Register tmp1 = locs()->in(1).reg();
-    Register tmp2 = locs()->temp(1).reg();
+    const Register tmp1 = locs()->in(1).reg();
+    const Register tmp2 = locs()->temp(1).reg();
     EmitJavascriptIntOverflowCheck(compiler, deopt, out, tmp1, tmp2);
   }
 }
 
 
 LocationSummary* UnaryMintOpInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps =
       FLAG_throw_on_javascript_int_overflow ? 2 : 0;
   LocationSummary* summary =
       new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
   summary->set_in(0, Location::RequiresFpuRegister());
   summary->set_out(0, Location::RequiresFpuRegister());
   if (FLAG_throw_on_javascript_int_overflow) {
     summary->set_temp(0, Location::RequiresRegister());
     summary->set_temp(1, Location::RequiresRegister());
   }
   return summary;
 }
 
 
 void UnaryMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT(op_kind() == Token::kBIT_NOT);
-  QRegister value = locs()->in(0).fpu_reg();
-  QRegister out = locs()->out(0).fpu_reg();
+  const QRegister value = locs()->in(0).fpu_reg();
+  const QRegister out = locs()->out(0).fpu_reg();
   Label* deopt = NULL;
   if (FLAG_throw_on_javascript_int_overflow) {
     deopt = compiler->AddDeoptStub(deopt_id(), ICData::kDeoptUnaryMintOp);
   }
   __ vmvnq(out, value);
   if (FLAG_throw_on_javascript_int_overflow) {
-    Register tmp1 = locs()->temp(0).reg();
-    Register tmp2 = locs()->temp(1).reg();
+    const Register tmp1 = locs()->temp(0).reg();
+    const Register tmp2 = locs()->temp(1).reg();
     EmitJavascriptIntOverflowCheck(compiler, deopt, out, tmp1, tmp2);
   }
 }
 
 
 LocationSummary* ThrowInstr::MakeLocationSummary(bool opt) const {
   return new LocationSummary(0, 0, LocationSummary::kCall);
 }
 
 
@@ skipping 139 matching lines @@
 }
 
 
 void StrictCompareInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   ASSERT(kind() == Token::kEQ_STRICT || kind() == Token::kNE_STRICT);
 
   // The ARM code does not use true- and false-labels here.
   BranchLabels labels = { NULL, NULL, NULL };
   Condition true_condition = EmitComparisonCode(compiler, labels);
 
-  Register result = locs()->out(0).reg();
+  const Register result = locs()->out(0).reg();
   __ LoadObject(result, Bool::True(), true_condition);
   __ LoadObject(result, Bool::False(), NegateCondition(true_condition));
 }
 
 
 void StrictCompareInstr::EmitBranchCode(FlowGraphCompiler* compiler,
                                         BranchInstr* branch) {
   ASSERT(kind() == Token::kEQ_STRICT || kind() == Token::kNE_STRICT);
 
   BranchLabels labels = compiler->CreateBranchLabels(branch);
   Condition true_condition = EmitComparisonCode(compiler, labels);
   EmitBranchOnCondition(compiler, true_condition, labels);
 }
 
 
 LocationSummary* BooleanNegateInstr::MakeLocationSummary(bool opt) const {
   return LocationSummary::Make(1,
                                Location::RequiresRegister(),
                                LocationSummary::kNoCall);
 }
 
 
 void BooleanNegateInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
-  Register value = locs()->in(0).reg();
-  Register result = locs()->out(0).reg();
+  const Register value = locs()->in(0).reg();
+  const Register result = locs()->out(0).reg();
 
   __ LoadObject(result, Bool::True());
   __ cmp(result, ShifterOperand(value));
   __ LoadObject(result, Bool::False(), EQ);
 }
 
 
 LocationSummary* AllocateObjectInstr::MakeLocationSummary(bool opt) const {
   return MakeCallSummary();
 }
 
 
 void AllocateObjectInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   const Code& stub = Code::Handle(StubCode::GetAllocationStubForClass(cls()));
   const ExternalLabel label(cls().ToCString(), stub.EntryPoint());
   compiler->GenerateCall(token_pos(),
                          &label,
                          PcDescriptors::kOther,
                          locs());
   __ Drop(ArgumentCount());  // Discard arguments.
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM