[ia32][wasm] Add I8x16/I16x8 Splat/ExtractLane/ReplaceLane

src/compiler/ia32/instruction-codes-ia32.h

Index: src/compiler/ia32/instruction-codes-ia32.h
diff --git a/src/compiler/ia32/instruction-codes-ia32.h b/src/compiler/ia32/instruction-codes-ia32.h
index af4241c1f17c4d3ebdc06f1c33c3d5e4d945f2d8..8127be244cdb5e269b163b58b4f857ad9b034933 100644
--- a/src/compiler/ia32/instruction-codes-ia32.h
+++ b/src/compiler/ia32/instruction-codes-ia32.h
@@ -113,12 +113,20 @@ namespace compiler {
   V(IA32StackCheck)                \
   V(IA32I32x4Splat)                \
   V(IA32I32x4ExtractLane)          \
+  V(IA32I16x8Splat)                \
+  V(IA32I16x8ExtractLane)          \
+  V(IA32I8x16Splat)                \
+  V(IA32I8x16ExtractLane)          \
   V(SSEI32x4ReplaceLane)           \

[bbudge, 2017/06/13 22:08:21]

Could you order the opcodes as they are in wasm-opcodes.h? There, they are
ordered primarily by vector type, number of parameters, etc., so for example,
I32x4ReplaceLane would follow I32x4ExtractLane.

   V(SSEI32x4Add)                   \
   V(SSEI32x4Sub)                   \
+  V(SSEI16x8ReplaceLane)           \
+  V(SSEI8x16ReplaceLane)           \
   V(AVXI32x4ReplaceLane)           \
   V(AVXI32x4Add)                   \
-  V(AVXI32x4Sub)
+  V(AVXI32x4Sub)                   \
+  V(AVXI16x8ReplaceLane)           \
+  V(AVXI8x16ReplaceLane)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes