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Side by Side Diff: src/ia32/macro-assembler-ia32.h

Issue 2937653002: [ia32][wasm] Add I8x16/I16x8 Splat/ExtractLane/ReplaceLane (Closed)
Patch Set: Rebase 2 Created 3 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_IA32_MACRO_ASSEMBLER_IA32_H_ 5 #ifndef V8_IA32_MACRO_ASSEMBLER_IA32_H_
6 #define V8_IA32_MACRO_ASSEMBLER_IA32_H_ 6 #define V8_IA32_MACRO_ASSEMBLER_IA32_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/bailout-reason.h" 9 #include "src/bailout-reason.h"
10 #include "src/frames.h" 10 #include "src/frames.h"
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716 } \ 716 } \
717 } 717 }
718 718
719 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register) 719 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register)
720 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, const Operand&) 720 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, const Operand&)
721 AVX_OP2_WITH_TYPE(Movd, movd, Register, XMMRegister) 721 AVX_OP2_WITH_TYPE(Movd, movd, Register, XMMRegister)
722 AVX_OP2_WITH_TYPE(Movd, movd, const Operand&, XMMRegister) 722 AVX_OP2_WITH_TYPE(Movd, movd, const Operand&, XMMRegister)
723 723
724 #undef AVX_OP2_WITH_TYPE 724 #undef AVX_OP2_WITH_TYPE
725 725
726 void Pxor(XMMRegister dst, XMMRegister src) { Pxor(dst, Operand(src)); }
727 void Pxor(XMMRegister dst, const Operand& src);
728
729 void Pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
730 Pshuflw(dst, Operand(src), shuffle);
731 }
732 void Pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle);
726 void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) { 733 void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
727 Pshufd(dst, Operand(src), shuffle); 734 Pshufd(dst, Operand(src), shuffle);
728 } 735 }
729 void Pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle); 736 void Pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle);
730 737
731 // Non-SSE2 instructions. 738 // Non-SSE2 instructions.
739 void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, Operand(src)); }
740 void Pshufb(XMMRegister dst, const Operand& src);
741
742 void Pextrb(Register dst, XMMRegister src, int8_t imm8);
743 void Pextrw(Register dst, XMMRegister src, int8_t imm8);
732 void Pextrd(Register dst, XMMRegister src, int8_t imm8); 744 void Pextrd(Register dst, XMMRegister src, int8_t imm8);
733 void Pinsrd(XMMRegister dst, Register src, int8_t imm8, 745 void Pinsrd(XMMRegister dst, Register src, int8_t imm8,
734 bool is_64_bits = false) { 746 bool is_64_bits = false) {
735 Pinsrd(dst, Operand(src), imm8, is_64_bits); 747 Pinsrd(dst, Operand(src), imm8, is_64_bits);
736 } 748 }
737 void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8, 749 void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8,
738 bool is_64_bits = false); 750 bool is_64_bits = false);
739 751
740 void Lzcnt(Register dst, Register src) { Lzcnt(dst, Operand(src)); } 752 void Lzcnt(Register dst, Register src) { Lzcnt(dst, Operand(src)); }
741 void Lzcnt(Register dst, const Operand& src); 753 void Lzcnt(Register dst, const Operand& src);
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955 inline Operand NativeContextOperand() { 967 inline Operand NativeContextOperand() {
956 return ContextOperand(esi, Context::NATIVE_CONTEXT_INDEX); 968 return ContextOperand(esi, Context::NATIVE_CONTEXT_INDEX);
957 } 969 }
958 970
959 #define ACCESS_MASM(masm) masm-> 971 #define ACCESS_MASM(masm) masm->
960 972
961 } // namespace internal 973 } // namespace internal
962 } // namespace v8 974 } // namespace v8
963 975
964 #endif // V8_IA32_MACRO_ASSEMBLER_IA32_H_ 976 #endif // V8_IA32_MACRO_ASSEMBLER_IA32_H_
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