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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
| 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
| (...skipping 96 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 107 V(IA32BitcastIF) \ | 107 V(IA32BitcastIF) \ |
| 108 V(IA32Lea) \ | 108 V(IA32Lea) \ |
| 109 V(IA32Push) \ | 109 V(IA32Push) \ |
| 110 V(IA32PushFloat32) \ | 110 V(IA32PushFloat32) \ |
| 111 V(IA32PushFloat64) \ | 111 V(IA32PushFloat64) \ |
| 112 V(IA32Poke) \ | 112 V(IA32Poke) \ |
| 113 V(IA32StackCheck) \ | 113 V(IA32StackCheck) \ |
| 114 V(IA32I32x4Splat) \ | 114 V(IA32I32x4Splat) \ |
| 115 V(IA32I32x4ExtractLane) \ | 115 V(IA32I32x4ExtractLane) \ |
| 116 V(SSEI32x4ReplaceLane) \ | 116 V(SSEI32x4ReplaceLane) \ |
| 117 V(AVXI32x4ReplaceLane) \ |
| 117 V(SSEI32x4Add) \ | 118 V(SSEI32x4Add) \ |
| 119 V(AVXI32x4Add) \ |
| 118 V(SSEI32x4Sub) \ | 120 V(SSEI32x4Sub) \ |
| 119 V(AVXI32x4ReplaceLane) \ | 121 V(AVXI32x4Sub) \ |
| 120 V(AVXI32x4Add) \ | 122 V(IA32I16x8Splat) \ |
| 121 V(AVXI32x4Sub) | 123 V(IA32I16x8ExtractLane) \ |
| 124 V(SSEI16x8ReplaceLane) \ |
| 125 V(AVXI16x8ReplaceLane) \ |
| 126 V(IA32I8x16Splat) \ |
| 127 V(IA32I8x16ExtractLane) \ |
| 128 V(SSEI8x16ReplaceLane) \ |
| 129 V(AVXI8x16ReplaceLane) |
| 122 | 130 |
| 123 // Addressing modes represent the "shape" of inputs to an instruction. | 131 // Addressing modes represent the "shape" of inputs to an instruction. |
| 124 // Many instructions support multiple addressing modes. Addressing modes | 132 // Many instructions support multiple addressing modes. Addressing modes |
| 125 // are encoded into the InstructionCode of the instruction and tell the | 133 // are encoded into the InstructionCode of the instruction and tell the |
| 126 // code generator after register allocation which assembler method to call. | 134 // code generator after register allocation which assembler method to call. |
| 127 // | 135 // |
| 128 // We use the following local notation for addressing modes: | 136 // We use the following local notation for addressing modes: |
| 129 // | 137 // |
| 130 // M = memory operand | 138 // M = memory operand |
| 131 // R = base register | 139 // R = base register |
| (...skipping 19 matching lines...) Expand all Loading... |
| 151 V(M2I) /* [ %r2*2 + K] */ \ | 159 V(M2I) /* [ %r2*2 + K] */ \ |
| 152 V(M4I) /* [ %r2*4 + K] */ \ | 160 V(M4I) /* [ %r2*4 + K] */ \ |
| 153 V(M8I) /* [ %r2*8 + K] */ \ | 161 V(M8I) /* [ %r2*8 + K] */ \ |
| 154 V(MI) /* [ K] */ | 162 V(MI) /* [ K] */ |
| 155 | 163 |
| 156 } // namespace compiler | 164 } // namespace compiler |
| 157 } // namespace internal | 165 } // namespace internal |
| 158 } // namespace v8 | 166 } // namespace v8 |
| 159 | 167 |
| 160 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ | 168 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ |
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