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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_IA32_MACRO_ASSEMBLER_IA32_H_ | 5 #ifndef V8_IA32_MACRO_ASSEMBLER_IA32_H_ |
| 6 #define V8_IA32_MACRO_ASSEMBLER_IA32_H_ | 6 #define V8_IA32_MACRO_ASSEMBLER_IA32_H_ |
| 7 | 7 |
| 8 #include "src/assembler.h" | 8 #include "src/assembler.h" |
| 9 #include "src/bailout-reason.h" | 9 #include "src/bailout-reason.h" |
| 10 #include "src/frames.h" | 10 #include "src/frames.h" |
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| 726 } \ | 726 } \ |
| 727 } | 727 } |
| 728 | 728 |
| 729 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register) | 729 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register) |
| 730 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, const Operand&) | 730 AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, const Operand&) |
| 731 AVX_OP2_WITH_TYPE(Movd, movd, Register, XMMRegister) | 731 AVX_OP2_WITH_TYPE(Movd, movd, Register, XMMRegister) |
| 732 AVX_OP2_WITH_TYPE(Movd, movd, const Operand&, XMMRegister) | 732 AVX_OP2_WITH_TYPE(Movd, movd, const Operand&, XMMRegister) |
| 733 | 733 |
| 734 #undef AVX_OP2_WITH_TYPE | 734 #undef AVX_OP2_WITH_TYPE |
| 735 | 735 |
| 736 void Pxor(XMMRegister dst, XMMRegister src) { Pxor(dst, Operand(src)); } |
| 737 void Pxor(XMMRegister dst, const Operand& src); |
| 738 |
| 739 void Pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) { |
| 740 Pshuflw(dst, Operand(src), shuffle); |
| 741 } |
| 742 void Pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle); |
| 736 void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) { | 743 void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) { |
| 737 Pshufd(dst, Operand(src), shuffle); | 744 Pshufd(dst, Operand(src), shuffle); |
| 738 } | 745 } |
| 739 void Pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle); | 746 void Pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle); |
| 740 | 747 |
| 741 // Non-SSE2 instructions. | 748 // Non-SSE2 instructions. |
| 749 void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, Operand(src)); } |
| 750 void Pshufb(XMMRegister dst, const Operand& src); |
| 751 |
| 752 void Pextrb(Register dst, XMMRegister src, int8_t imm8); |
| 753 void Pextrw(Register dst, XMMRegister src, int8_t imm8); |
| 742 void Pextrd(Register dst, XMMRegister src, int8_t imm8); | 754 void Pextrd(Register dst, XMMRegister src, int8_t imm8); |
| 743 void Pinsrd(XMMRegister dst, Register src, int8_t imm8, | 755 void Pinsrd(XMMRegister dst, Register src, int8_t imm8, |
| 744 bool is_64_bits = false) { | 756 bool is_64_bits = false) { |
| 745 Pinsrd(dst, Operand(src), imm8, is_64_bits); | 757 Pinsrd(dst, Operand(src), imm8, is_64_bits); |
| 746 } | 758 } |
| 747 void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8, | 759 void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8, |
| 748 bool is_64_bits = false); | 760 bool is_64_bits = false); |
| 749 | 761 |
| 750 void Lzcnt(Register dst, Register src) { Lzcnt(dst, Operand(src)); } | 762 void Lzcnt(Register dst, Register src) { Lzcnt(dst, Operand(src)); } |
| 751 void Lzcnt(Register dst, const Operand& src); | 763 void Lzcnt(Register dst, const Operand& src); |
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| 965 inline Operand NativeContextOperand() { | 977 inline Operand NativeContextOperand() { |
| 966 return ContextOperand(esi, Context::NATIVE_CONTEXT_INDEX); | 978 return ContextOperand(esi, Context::NATIVE_CONTEXT_INDEX); |
| 967 } | 979 } |
| 968 | 980 |
| 969 #define ACCESS_MASM(masm) masm-> | 981 #define ACCESS_MASM(masm) masm-> |
| 970 | 982 |
| 971 } // namespace internal | 983 } // namespace internal |
| 972 } // namespace v8 | 984 } // namespace v8 |
| 973 | 985 |
| 974 #endif // V8_IA32_MACRO_ASSEMBLER_IA32_H_ | 986 #endif // V8_IA32_MACRO_ASSEMBLER_IA32_H_ |
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