[ARM64] Support 128 bit moves and swaps in code generator.

src/compiler/arm64/code-generator-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm64/assembler-arm64-inl.h"
 #include "src/arm64/frames-arm64.h"
 #include "src/arm64/macro-assembler-arm64-inl.h"
 #include "src/compilation-info.h"
@@ skipping 2211 matching lines @@
         }
       }
     }
   } else if (source->IsFPRegister()) {
     VRegister src = g.ToDoubleRegister(source);
     if (destination->IsFPRegister()) {
       VRegister dst = g.ToDoubleRegister(destination);
       __ Fmov(dst, src);
     } else {
       DCHECK(destination->IsFPStackSlot());
-      __ Str(src, g.ToMemOperand(destination, masm()));
+      MemOperand dst = g.ToMemOperand(destination, masm());
+      if (!destination->IsSimd128StackSlot()) {
+        __ Str(src, dst);
+      } else {
+        __ st1(src, dst);

[martyn.capewell, 2017/06/08 08:29:13]

I'm not sure this will work - I think ToDoubleRegister returns a D-sized
VRegister, so both sides of this conditional store 64 bits from src to dst, but
with different instructions.

On ARM64, the normal Ldr and Str methods support Q registers, so something like
this might work:
VRegister src = (destination->IsSimd128StackSlot) ? g.ToSimd128Register() :
g.ToDoubleRegister();
__ Str(src, dst);

Alternatively, as the way VRegisters overlay is different in ARM64, the size
modifiers could be applied, eg. src.Q().

[bbudge, 2017/06/08 20:16:59]

I forgot that VRegisters have a size. I think your alternative solution is the
only one that would work, as ToSimd128Register calls VRegister::from_code, which
assumes it's a d-register. Done here and below.

+      }
     }
   } else if (source->IsFPStackSlot()) {
     DCHECK(destination->IsFPRegister() || destination->IsFPStackSlot());
     MemOperand src = g.ToMemOperand(source, masm());
     if (destination->IsFPRegister()) {
-      __ Ldr(g.ToDoubleRegister(destination), src);
+      VRegister dst = g.ToDoubleRegister(destination);
+      if (!destination->IsSimd128Register()) {
+        __ Ldr(dst, src);
+      } else {
+        __ ld1(dst, src);
+      }
     } else {
       UseScratchRegisterScope scope(masm());
       VRegister temp = scope.AcquireD();
-      __ Ldr(temp, src);
-      __ Str(temp, g.ToMemOperand(destination, masm()));
+      MemOperand dst = g.ToMemOperand(destination, masm());
+      if (!destination->IsSimd128StackSlot()) {
+        __ Ldr(temp, src);
+        __ Str(temp, dst);
+      } else {
+        __ ld1(temp, src);
+        __ st1(temp, dst);
+      }
     }
   } else {
     UNREACHABLE();
   }
 }
 
 
 void CodeGenerator::AssembleSwap(InstructionOperand* source,
                                  InstructionOperand* destination) {
   Arm64OperandConverter g(this, nullptr);
@@ skipping 11 matching lines @@
       __ Mov(dst, temp);
     } else {
       DCHECK(destination->IsStackSlot());
       MemOperand dst = g.ToMemOperand(destination, masm());
       __ Mov(temp, src);
       __ Ldr(src, dst);
       __ Str(temp, dst);
     }
   } else if (source->IsStackSlot() || source->IsFPStackSlot()) {
     UseScratchRegisterScope scope(masm());
-    DoubleRegister temp_0 = scope.AcquireD();
-    DoubleRegister temp_1 = scope.AcquireD();
+    VRegister temp_0 = scope.AcquireD();
+    VRegister temp_1 = scope.AcquireD();
     MemOperand src = g.ToMemOperand(source, masm());
     MemOperand dst = g.ToMemOperand(destination, masm());
-    __ Ldr(temp_0, src);
-    __ Ldr(temp_1, dst);
-    __ Str(temp_0, dst);
-    __ Str(temp_1, src);
+    if (!source->IsSimd128StackSlot()) {
+      __ Ldr(temp_0, src);
+      __ Ldr(temp_1, dst);
+      __ Str(temp_0, dst);
+      __ Str(temp_1, src);
+    } else {
+      __ ld1(temp_0, src);
+      __ ld1(temp_1, dst);
+      __ st1(temp_0, dst);
+      __ st1(temp_1, src);
+    }
   } else if (source->IsFPRegister()) {
     UseScratchRegisterScope scope(masm());
     VRegister temp = scope.AcquireD();
     VRegister src = g.ToDoubleRegister(source);
     if (destination->IsFPRegister()) {
       VRegister dst = g.ToDoubleRegister(destination);
       __ Fmov(temp, src);
       __ Fmov(src, dst);
       __ Fmov(dst, temp);
     } else {
       DCHECK(destination->IsFPStackSlot());
       MemOperand dst = g.ToMemOperand(destination, masm());
-      __ Fmov(temp, src);
-      __ Ldr(src, dst);
-      __ Str(temp, dst);
+      if (!source->IsSimd128Register()) {
+        __ Fmov(temp, src);
+        __ Ldr(src, dst);
+        __ Str(temp, dst);
+      } else {
+        __ Fmov(temp, src);
+        __ ld1(src, dst);
+        __ st1(temp, dst);
+      }
     }
   } else {
     // No other combinations are possible.
     UNREACHABLE();
   }
 }
 
 
 void CodeGenerator::AssembleJumpTable(Label** targets, size_t target_count) {
   // On 64-bit ARM we emit the jump tables inline.
@@ skipping 22 matching lines @@
       padding_size -= kInstructionSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8