Allows unboxed doubles to be disabled.

runtime/vm/flow_graph_compiler_arm.cc

Index: runtime/vm/flow_graph_compiler_arm.cc
===================================================================
--- runtime/vm/flow_graph_compiler_arm.cc	(revision 36258)
+++ runtime/vm/flow_graph_compiler_arm.cc	(working copy)
@@ -24,6 +24,7 @@
 
 DEFINE_FLAG(bool, trap_on_deoptimization, false, "Trap on deoptimization.");
 DEFINE_FLAG(bool, unbox_mints, true, "Optimize 64-bit integer arithmetic.");
+DEFINE_FLAG(bool, unbox_doubles, true, "Optimize double arithmetic.");
 DECLARE_FLAG(int, optimization_counter_threshold);
 DECLARE_FLAG(int, reoptimization_counter_threshold);
 DECLARE_FLAG(bool, enable_type_checks);
@@ -40,6 +41,11 @@
 }
 
 
+bool FlowGraphCompiler::SupportsUnboxedDoubles() {
+  return TargetCPUFeatures::vfp_supported() && FLAG_unbox_doubles;
+}
+
+
 bool FlowGraphCompiler::SupportsUnboxedMints() {
   return TargetCPUFeatures::neon_supported() && FLAG_unbox_mints;
 }
@@ -1596,7 +1602,14 @@
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
-      __ vmovq(destination.fpu_reg(), source.fpu_reg());
+      if (TargetCPUFeatures::neon_supported()) {
+        __ vmovq(destination.fpu_reg(), source.fpu_reg());
+      } else {
+        // If we're not inlining simd values, then only the even numbered D
+        // register will have anything in them.
+        __ vmovd(EvenDRegisterOf(destination.fpu_reg()),
+                 EvenDRegisterOf(source.fpu_reg()));
+      }
     } else {
       if (destination.IsDoubleStackSlot()) {
         const intptr_t dest_offset = destination.ToStackSlotOffset();