[arm64] Fix assertion in IsImmLLiteral and enable literal pool tests.

test/cctest/test-disasm-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1465 matching lines @@
   COMPARE(ldaxrb(wzr, csp), "ldaxrb wzr, [csp]");
   COMPARE(ldaxrh(wzr, csp), "ldaxrh wzr, [csp]");
   COMPARE(ldaxr(wzr, csp), "ldaxr wzr, [csp]");
   COMPARE(stlxrb(wzr, wzr, csp), "stlxrb wzr, wzr, [csp]");
   COMPARE(stlxrh(wzr, wzr, csp), "stlxrh wzr, wzr, [csp]");
   COMPARE(stlxr(wzr, wzr, csp), "stlxr wzr, wzr, [csp]");
 
   CLEANUP();
 }
 
-#if 0  // TODO(all): enable.
 TEST_(load_literal) {
   SET_UP_ASM();
 
-  COMPARE_PREFIX(ldr(x10, 0x1234567890abcdefUL),  "ldr x10, pc+8");
-  COMPARE_PREFIX(ldr(w20, 0xfedcba09),  "ldr w20, pc+8");
-  COMPARE_PREFIX(ldr(d11, 1.234),  "ldr d11, pc+8");
-  COMPARE_PREFIX(ldr(s22, 2.5f),  "ldr s22, pc+8");
+  COMPARE_PREFIX(ldr_pcrel(x10, 0), "ldr x10, pc+0");
+  COMPARE_PREFIX(ldr_pcrel(x10, 1), "ldr x10, pc+4");
+  COMPARE_PREFIX(ldr_pcrel(d11, 0), "ldr d11, pc+0");
+  COMPARE_PREFIX(ldr_pcrel(d11, 1), "ldr d11, pc+4");
+
+  int max_offset = (kMaxLoadLiteralRange >> kLoadLiteralScaleLog2) - 1;
+  COMPARE_PREFIX(ldr_pcrel(x0, max_offset), "ldr x0, pc+1048572");
+  COMPARE_PREFIX(ldr_pcrel(d0, max_offset), "ldr d0, pc+1048572");
 
   CLEANUP();
 }
-#endif
 
 TEST_(cond_select) {
   SET_UP_ASM();
 
   COMPARE(csel(w0, w1, w2, eq), "csel w0, w1, w2, eq");
   COMPARE(csel(x3, x4, x5, ne), "csel x3, x4, x5, ne");
   COMPARE(csinc(w6, w7, w8, hs), "csinc w6, w7, w8, hs");
   COMPARE(csinc(x9, x10, x11, lo), "csinc x9, x10, x11, lo");
   COMPARE(csinv(w12, w13, w14, mi), "csinv w12, w13, w14, mi");
   COMPARE(csinv(x15, x16, x17, pl), "csinv x15, x16, x17, pl");
@@ skipping 3422 matching lines @@
   COMPARE(Fcvtzs(d8, d6, 34), "fcvtzs d8, d6, #34");
 
   COMPARE(Fcvtzu(v5.V2S(), v3.V2S(), 11), "fcvtzu v5.2s, v3.2s, #11");
   COMPARE(Fcvtzu(v6.V4S(), v4.V4S(), 12), "fcvtzu v6.4s, v4.4s, #12");
   COMPARE(Fcvtzu(v7.V2D(), v5.V2D(), 33), "fcvtzu v7.2d, v5.2d, #33");
   COMPARE(Fcvtzu(s8, s6, 13), "fcvtzu s8, s6, #13");
   COMPARE(Fcvtzu(d8, d6, 34), "fcvtzu d8, d6, #34");
 
   CLEANUP();
 }