[arm64] Fix pre-shifted immediate generation involving csp.

test/cctest/test-assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 7135 matching lines @@
 
   RUN();
 
   CHECK_EQUAL_64(0, x0);
   CHECK_EQUAL_64(0, x1);
   CHECK_EQUAL_64(0, x2);
 
   TEARDOWN();
 }
 
+TEST(preshift_immediates) {
+  INIT_V8();
+  SETUP();
+
+  START();
+  // Test operations involving immediates that could be generated using a
+  // pre-shifted encodable immediate followed by a post-shift applied to
+  // the arithmetic or logical operation.
+
+  // Save csp.
+  __ Mov(x29, csp);
+
+  // Set the registers to known values.
+  __ Mov(x0, 0x1000);
+  __ Mov(csp, 0x1000);
+
+  // Arithmetic ops.
+  __ Add(x1, x0, 0x1f7de);

[Tobias Tebbi, 2017/06/08 10:27:51]

How are these constants encodable with a shift? They do not have trailing zeros.

[martyn.capewell, 2017/06/08 10:37:17]

In order to improve "encodability", ones are inserted on left shifting the
target immediate, which are removed again on right shift. So 0xffffff1 becomes:
 mov w16, #0xffffff1f
 add w2, w0, w16, lsr #4

0xffffff1f is encodable as a logical immediate, but 0xffffff10 is not.

The idea is to create a string of bits that wrap around the target register,
such that the rotation applied in logical immediate generation is more
effective.

+  __ Add(w2, w0, 0xffffff1);
+  __ Adds(x3, x0, 0x18001);
+  __ Adds(w4, w0, 0xffffff1);
+  __ Sub(x5, x0, 0x1f7de);
+  __ Sub(w6, w0, 0xffffff1);
+  __ Subs(x7, x0, 0x18001);
+  __ Subs(w8, w0, 0xffffff1);
+
+  // Logical ops.
+  __ And(x9, x0, 0x1f7de);
+  __ Orr(w10, w0, 0xffffff1);
+  __ Eor(x11, x0, 0x18001);
+
+  // Ops using the stack pointer.
+  __ Add(csp, csp, 0x1f7f0);
+  __ Mov(x12, csp);
+  __ Mov(csp, 0x1000);
+
+  __ Adds(x13, csp, 0x1f7f0);
+
+  __ Orr(csp, x0, 0x1f7f0);
+  __ Mov(x14, csp);
+
+  //  Restore csp.
+  __ Mov(csp, x29);
+  END();
+
+  RUN();
+
+  CHECK_EQUAL_64(0x1000, x0);
+  CHECK_EQUAL_64(0x207de, x1);
+  CHECK_EQUAL_64(0x10000ff1, x2);
+  CHECK_EQUAL_64(0x19001, x3);
+  CHECK_EQUAL_64(0x10000ff1, x4);
+  CHECK_EQUAL_64(0xfffffffffffe1822, x5);
+  CHECK_EQUAL_64(0xf000100f, x6);
+  CHECK_EQUAL_64(0xfffffffffffe8fff, x7);
+  CHECK_EQUAL_64(0xf000100f, x8);
+  CHECK_EQUAL_64(0x1000, x9);
+  CHECK_EQUAL_64(0xffffff1, x10);
+  CHECK_EQUAL_64(0x207f0, x12);
+  CHECK_EQUAL_64(0x207f0, x13);
+  CHECK_EQUAL_64(0x1f7f0, x14);
+
+  TEARDOWN();
+}
 
 TEST(claim_drop_zero) {
   INIT_V8();
   SETUP();
 
   START();
 
   Label start;
   __ Bind(&start);
   __ Claim(0);
@@ skipping 8270 matching lines @@
   __ Mov(x0, 1);
 
   END();
 
   RUN();
 
   CHECK_EQUAL_64(0x1, x0);
 
   TEARDOWN();
 }