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Unified Diff: src/s390/assembler-s390.cc

Issue 2921473003: PPC/S390: [compiler] Delay allocation of code-embedded heap numbers.
Patch Set: additional changes for s390 Created 3 years, 7 months ago
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Index: src/s390/assembler-s390.cc
diff --git a/src/s390/assembler-s390.cc b/src/s390/assembler-s390.cc
index 35305fc07487b8507b0e6483f9cc5c04efade2d7..5fbe03d1699863d60a737d60ef62e793742c8d1d 100644
--- a/src/s390/assembler-s390.cc
+++ b/src/s390/assembler-s390.cc
@@ -313,15 +313,24 @@ Operand::Operand(Handle<Object> handle) {
// Verify all Objects referred by code are NOT in new space.
Object* obj = *handle;
if (obj->IsHeapObject()) {
- imm_ = reinterpret_cast<intptr_t>(handle.location());
+ value_.immediate = reinterpret_cast<intptr_t>(handle.location());
rmode_ = RelocInfo::EMBEDDED_OBJECT;
} else {
// no relocation needed
- imm_ = reinterpret_cast<intptr_t>(obj);
+ value_.immediate = reinterpret_cast<intptr_t>(obj);
rmode_ = kRelocInfo_NONEPTR;
}
}
+Operand Operand::EmbeddedNumber(double value) {
+ int32_t smi;
+ if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
+ Operand result(0, RelocInfo::EMBEDDED_OBJECT);
+ result.is_heap_number_ = true;
+ result.value_.heap_number = value;
+ return result;
+}
+
MemOperand::MemOperand(Register rn, int32_t offset) {
baseRegister = rn;
indexRegister = r0;
@@ -348,9 +357,11 @@ Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
relocations_.reserve(128);
}
-void Assembler::GetCode(CodeDesc* desc) {
+void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
EmitRelocations();
+ AllocateRequestedHeapNumbers(isolate);
+
// Set up code descriptor.
desc->buffer = buffer_;
desc->buffer_size = buffer_size_;
@@ -651,9 +662,9 @@ void Assembler::nop(int type) {
void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) {
DCHECK(is_uint12(op));
- DCHECK(is_uint16(i2.imm_) || is_int16(i2.imm_));
+ DCHECK(is_uint16(i2.immediate()) || is_int16(i2.immediate()));
emit4bytes((op & 0xFF0) * B20 | r1.code() * B20 | (op & 0xF) * B16 |
- (i2.imm_ & 0xFFFF));
+ (i2.immediate() & 0xFFFF));
}
// RI2 format: <insn> M1,I2
@@ -667,9 +678,9 @@ void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) {
void Assembler::ri_form(Opcode op, Condition m1, const Operand& i2) {
DCHECK(is_uint12(op));
DCHECK(is_uint4(m1));
- DCHECK(op == BRC ? is_int16(i2.imm_) : is_uint16(i2.imm_));
+ DCHECK(op == BRC ? is_int16(i2.immediate()) : is_uint16(i2.immediate()));
emit4bytes((op & 0xFF0) * B20 | m1 * B20 | (op & 0xF) * B16 |
- (i2.imm_ & 0xFFFF));
+ (i2.immediate() & 0xFFFF));
}
// RIE-f format: <insn> R1,R2,I3,I4,I5
@@ -681,15 +692,15 @@ void Assembler::rie_f_form(Opcode op, Register r1, Register r2,
const Operand& i3, const Operand& i4,
const Operand& i5) {
DCHECK(is_uint16(op));
- DCHECK(is_uint8(i3.imm_));
- DCHECK(is_uint8(i4.imm_));
- DCHECK(is_uint8(i5.imm_));
+ DCHECK(is_uint8(i3.immediate()));
+ DCHECK(is_uint8(i4.immediate()));
+ DCHECK(is_uint8(i5.immediate()));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
(static_cast<uint64_t>(r1.code())) * B36 |
(static_cast<uint64_t>(r2.code())) * B32 |
- (static_cast<uint64_t>(i3.imm_)) * B24 |
- (static_cast<uint64_t>(i4.imm_)) * B16 |
- (static_cast<uint64_t>(i5.imm_)) * B8 |
+ (static_cast<uint64_t>(i3.immediate())) * B24 |
+ (static_cast<uint64_t>(i4.immediate())) * B16 |
+ (static_cast<uint64_t>(i5.immediate())) * B8 |
(static_cast<uint64_t>(op & 0x00FF));
emit6bytes(code);
}
@@ -707,11 +718,11 @@ void Assembler::rie_f_form(Opcode op, Register r1, Register r2,
void Assembler::rie_form(Opcode op, Register r1, Register r3,
const Operand& i2) {
DCHECK(is_uint16(op));
- DCHECK(is_int16(i2.imm_));
+ DCHECK(is_int16(i2.immediate()));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
(static_cast<uint64_t>(r1.code())) * B36 |
(static_cast<uint64_t>(r3.code())) * B32 |
- (static_cast<uint64_t>(i2.imm_ & 0xFFFF)) * B16 |
+ (static_cast<uint64_t>(i2.immediate() & 0xFFFF)) * B16 |
(static_cast<uint64_t>(op & 0x00FF));
emit6bytes(code);
}
@@ -768,8 +779,9 @@ void Assembler::rs_form(Opcode op, Register r1, Condition m3, Register b2,
void Assembler::rsi_form(Opcode op, Register r1, Register r3,
const Operand& i2) {
DCHECK(is_uint8(op));
- DCHECK(is_uint16(i2.imm_));
- emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 | (i2.imm_ & 0xFFFF));
+ DCHECK(is_uint16(i2.immediate()));
+ emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 |
+ (i2.immediate() & 0xFFFF));
}
// RSL format: <insn> R1,R3,D2(B2)
@@ -921,13 +933,13 @@ void Assembler::ris_form(Opcode op, Register r1, Condition m3, Register b4,
Disp d4, const Operand& i2) {
DCHECK(is_uint12(d4));
DCHECK(is_uint16(op));
- DCHECK(is_uint8(i2.imm_));
+ DCHECK(is_uint8(i2.immediate()));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
(static_cast<uint64_t>(r1.code())) * B36 |
(static_cast<uint64_t>(m3)) * B32 |
(static_cast<uint64_t>(b4.code())) * B28 |
(static_cast<uint64_t>(d4)) * B16 |
- (static_cast<uint64_t>(i2.imm_)) << 8 |
+ (static_cast<uint64_t>(i2.immediate())) << 8 |
(static_cast<uint64_t>(op & 0x00FF));
emit6bytes(code);
}
@@ -962,7 +974,7 @@ void Assembler::s_form(Opcode op, Register b1, Disp d2) {
}
void Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
- emit4bytes((op & 0x00FF) << 24 | i2.imm_ * B16 | b1.code() * B12 | d1);
+ emit4bytes((op & 0x00FF) << 24 | i2.immediate() * B16 | b1.code() * B12 | d1);
}
// SIY format: <insn> D1(B1),I2
@@ -981,9 +993,9 @@ void Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
DCHECK(is_uint20(d1) || is_int20(d1));
DCHECK(is_uint16(op));
- DCHECK(is_uint8(i2.imm_));
+ DCHECK(is_uint8(i2.immediate()));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
- (static_cast<uint64_t>(i2.imm_)) * B32 |
+ (static_cast<uint64_t>(i2.immediate())) * B32 |
(static_cast<uint64_t>(b1.code())) * B28 |
(static_cast<uint64_t>(d1 & 0x0FFF)) * B16 |
(static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 |
@@ -1007,11 +1019,11 @@ void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
void Assembler::sil_form(Opcode op, Register b1, Disp d1, const Operand& i2) {
DCHECK(is_uint12(d1));
DCHECK(is_uint16(op));
- DCHECK(is_uint16(i2.imm_));
+ DCHECK(is_uint16(i2.immediate()));
uint64_t code = (static_cast<uint64_t>(op)) * B32 |
(static_cast<uint64_t>(b1.code())) * B28 |
(static_cast<uint64_t>(d1)) * B16 |
- (static_cast<uint64_t>(i2.imm_));
+ (static_cast<uint64_t>(i2.immediate()));
emit6bytes(code);
}
@@ -1125,10 +1137,10 @@ void Assembler::ss_form(Opcode op, Length l1, const Operand& i3, Register b1,
DCHECK(is_uint12(d1));
DCHECK(is_uint8(op));
DCHECK(is_uint4(l1));
- DCHECK(is_uint4(i3.imm_));
+ DCHECK(is_uint4(i3.immediate()));
uint64_t code =
(static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 |
- (static_cast<uint64_t>(i3.imm_)) * B32 |
+ (static_cast<uint64_t>(i3.immediate())) * B32 |
(static_cast<uint64_t>(b1.code())) * B28 |
(static_cast<uint64_t>(d1)) * B16 |
(static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2));
@@ -1426,7 +1438,7 @@ void Assembler::risbg(Register dst, Register src, const Operand& startBit,
bool zeroBits) {
// High tag the top bit of I4/EndBit to zero out any unselected bits
if (zeroBits)
- rie_f_form(RISBG, dst, src, startBit, Operand(endBit.imm_ | 0x80),
+ rie_f_form(RISBG, dst, src, startBit, Operand(endBit.immediate() | 0x80),
shiftAmt);
else
rie_f_form(RISBG, dst, src, startBit, endBit, shiftAmt);
@@ -1438,7 +1450,7 @@ void Assembler::risbgn(Register dst, Register src, const Operand& startBit,
bool zeroBits) {
// High tag the top bit of I4/EndBit to zero out any unselected bits
if (zeroBits)
- rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.imm_ | 0x80),
+ rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.immediate() | 0x80),
shiftAmt);
else
rie_f_form(RISBGN, dst, src, startBit, endBit, shiftAmt);
@@ -1472,9 +1484,10 @@ void Assembler::ark(Register r1, Register r2, Register r3) {
// Add Storage-Imm (32)
void Assembler::asi(const MemOperand& opnd, const Operand& imm) {
- DCHECK(is_int8(imm.imm_));
+ DCHECK(is_int8(imm.immediate()));
DCHECK(is_int20(opnd.offset()));
- siy_form(ASI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset());
+ siy_form(ASI, Operand(0xff & imm.immediate()), opnd.rb(),
+ 0xfffff & opnd.offset());
}
// -----------------------
@@ -1495,9 +1508,10 @@ void Assembler::agrk(Register r1, Register r2, Register r3) {
// Add Storage-Imm (64)
void Assembler::agsi(const MemOperand& opnd, const Operand& imm) {
- DCHECK(is_int8(imm.imm_));
+ DCHECK(is_int8(imm.immediate()));
DCHECK(is_int20(opnd.offset()));
- siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset());
+ siy_form(AGSI, Operand(0xff & imm.immediate()), opnd.rb(),
+ 0xfffff & opnd.offset());
}
// -------------------------------
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