PPC/S390: [compiler] Delay allocation of code-embedded heap numbers.

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 295 matching lines @@
 // -----------------------------------------------------------------------------
 // Implementation of Operand and MemOperand
 // See assembler-s390-inl.h for inlined constructors
 
 Operand::Operand(Handle<Object> handle) {
   AllowDeferredHandleDereference using_raw_address;
   rm_ = no_reg;
   // Verify all Objects referred by code are NOT in new space.
   Object* obj = *handle;
   if (obj->IsHeapObject()) {
-    imm_ = reinterpret_cast<intptr_t>(handle.location());
+    value_.immediate = reinterpret_cast<intptr_t>(handle.location());
     rmode_ = RelocInfo::EMBEDDED_OBJECT;
   } else {
     // no relocation needed
-    imm_ = reinterpret_cast<intptr_t>(obj);
+    value_.immediate = reinterpret_cast<intptr_t>(obj);
     rmode_ = kRelocInfo_NONEPTR;
   }
 }
 
+Operand Operand::EmbeddedNumber(double value) {
+  int32_t smi;
+  if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
+  Operand result(0, RelocInfo::EMBEDDED_OBJECT);
+  result.is_heap_number_ = true;
+  result.value_.heap_number = value;
+  return result;
+}
+
 MemOperand::MemOperand(Register rn, int32_t offset) {
   baseRegister = rn;
   indexRegister = r0;
   offset_ = offset;
 }
 
 MemOperand::MemOperand(Register rx, Register rb, int32_t offset) {
   baseRegister = rb;
   indexRegister = rx;
   offset_ = offset;
 }
 
 // -----------------------------------------------------------------------------
 // Specific instructions, constants, and masks.
 
 Assembler::Assembler(IsolateData isolate_data, void* buffer, int buffer_size)
     : AssemblerBase(isolate_data, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
       code_targets_(100) {
   reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
 
   last_bound_pos_ = 0;
   ClearRecordedAstId();
   relocations_.reserve(128);
 }
 
-void Assembler::GetCode(CodeDesc* desc) {
+void Assembler::GetCode(Isolate* isolate, CodeDesc* desc) {
   EmitRelocations();
 
+  AllocateRequestedHeapNumbers(isolate);
+
   // Set up code descriptor.
   desc->buffer = buffer_;
   desc->buffer_size = buffer_size_;
   desc->instr_size = pc_offset();
   desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
   desc->origin = this;
   desc->unwinding_info_size = 0;
   desc->unwinding_info = nullptr;
 }
 
@@ skipping 280 matching lines @@
 // RI1 format: <insn> R1,I2
 //    +--------+----+----+------------------+
 //    | OpCode | R1 |OpCd|        I2        |
 //    +--------+----+----+------------------+
 //    0        8    12   16                31
 #define RI1_FORM_EMIT(name, op) \
   void Assembler::name(Register r, const Operand& i2) { ri_form(op, r, i2); }
 
 void Assembler::ri_form(Opcode op, Register r1, const Operand& i2) {
   DCHECK(is_uint12(op));
-  DCHECK(is_uint16(i2.imm_) || is_int16(i2.imm_));
+  DCHECK(is_uint16(i2.immediate()) || is_int16(i2.immediate()));
   emit4bytes((op & 0xFF0) * B20 | r1.code() * B20 | (op & 0xF) * B16 |
-             (i2.imm_ & 0xFFFF));
+             (i2.immediate() & 0xFFFF));
 }
 
 // RI2 format: <insn> M1,I2
 //    +--------+----+----+------------------+
 //    | OpCode | M1 |OpCd|        I2        |
 //    +--------+----+----+------------------+
 //    0        8    12   16                31
 #define RI2_FORM_EMIT(name, op) \
   void Assembler::name(Condition m, const Operand& i2) { ri_form(op, m, i2); }
 
 void Assembler::ri_form(Opcode op, Condition m1, const Operand& i2) {
   DCHECK(is_uint12(op));
   DCHECK(is_uint4(m1));
-  DCHECK(op == BRC ? is_int16(i2.imm_) : is_uint16(i2.imm_));
+  DCHECK(op == BRC ? is_int16(i2.immediate()) : is_uint16(i2.immediate()));
   emit4bytes((op & 0xFF0) * B20 | m1 * B20 | (op & 0xF) * B16 |
-             (i2.imm_ & 0xFFFF));
+             (i2.immediate() & 0xFFFF));
 }
 
 // RIE-f format: <insn> R1,R2,I3,I4,I5
 //    +--------+----+----+------------------+--------+--------+
 //    | OpCode | R1 | R2 |   I3   |    I4   |   I5   | OpCode |
 //    +--------+----+----+------------------+--------+--------+
 //    0        8    12   16      24         32       40      47
 void Assembler::rie_f_form(Opcode op, Register r1, Register r2,
                            const Operand& i3, const Operand& i4,
                            const Operand& i5) {
   DCHECK(is_uint16(op));
-  DCHECK(is_uint8(i3.imm_));
-  DCHECK(is_uint8(i4.imm_));
-  DCHECK(is_uint8(i5.imm_));
+  DCHECK(is_uint8(i3.immediate()));
+  DCHECK(is_uint8(i4.immediate()));
+  DCHECK(is_uint8(i5.immediate()));
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                   (static_cast<uint64_t>(r1.code())) * B36 |
                   (static_cast<uint64_t>(r2.code())) * B32 |
-                  (static_cast<uint64_t>(i3.imm_)) * B24 |
-                  (static_cast<uint64_t>(i4.imm_)) * B16 |
-                  (static_cast<uint64_t>(i5.imm_)) * B8 |
+                  (static_cast<uint64_t>(i3.immediate())) * B24 |
+                  (static_cast<uint64_t>(i4.immediate())) * B16 |
+                  (static_cast<uint64_t>(i5.immediate())) * B8 |
                   (static_cast<uint64_t>(op & 0x00FF));
   emit6bytes(code);
 }
 
 // RIE format: <insn> R1,R3,I2
 //    +--------+----+----+------------------+--------+--------+
 //    | OpCode | R1 | R3 |        I2        |////////| OpCode |
 //    +--------+----+----+------------------+--------+--------+
 //    0        8    12   16                 32       40      47
 #define RIE_FORM_EMIT(name, op)                                       \
   void Assembler::name(Register r1, Register r3, const Operand& i2) { \
     rie_form(op, r1, r3, i2);                                         \
   }
 
 void Assembler::rie_form(Opcode op, Register r1, Register r3,
                          const Operand& i2) {
   DCHECK(is_uint16(op));
-  DCHECK(is_int16(i2.imm_));
+  DCHECK(is_int16(i2.immediate()));
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                   (static_cast<uint64_t>(r1.code())) * B36 |
                   (static_cast<uint64_t>(r3.code())) * B32 |
-                  (static_cast<uint64_t>(i2.imm_ & 0xFFFF)) * B16 |
+                  (static_cast<uint64_t>(i2.immediate() & 0xFFFF)) * B16 |
                   (static_cast<uint64_t>(op & 0x00FF));
   emit6bytes(code);
 }
 
 // RS1 format: <insn> R1,R3,D2(B2)
 //    +--------+----+----+----+-------------+
 //    | OpCode | R1 | R3 | B2 |     D2      |
 //    +--------+----+----+----+-------------+
 //    0        8    12   16   20           31
 #define RS1_FORM_EMIT(name, op)                                            \
@@ skipping 36 matching lines @@
 //    +--------+----+----+------------------+
 //    0        8    12   16                 31
 #define RSI_FORM_EMIT(name, op)                                       \
   void Assembler::name(Register r1, Register r3, const Operand& i2) { \
     rsi_form(op, r1, r3, i2);                                         \
   }
 
 void Assembler::rsi_form(Opcode op, Register r1, Register r3,
                          const Operand& i2) {
   DCHECK(is_uint8(op));
-  DCHECK(is_uint16(i2.imm_));
-  emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 | (i2.imm_ & 0xFFFF));
+  DCHECK(is_uint16(i2.immediate()));
+  emit4bytes(op * B24 | r1.code() * B20 | r3.code() * B16 |
+             (i2.immediate() & 0xFFFF));
 }
 
 // RSL format: <insn> R1,R3,D2(B2)
 //    +--------+----+----+----+-------------+--------+--------+
 //    | OpCode | L1 |    | B2 |    D2       |        | OpCode |
 //    +--------+----+----+----+-------------+--------+--------+
 //    0        8    12   16   20            32       40      47
 #define RSL_FORM_EMIT(name, op)                           \
   void Assembler::name(Length l1, Register b2, Disp d2) { \
     rsl_form(op, l1, b2, d2);                             \
@@ skipping 131 matching lines @@
   }                                                                     \
   void Assembler::name(Register r1, const Operand& i2, Condition m3,    \
                        const MemOperand& opnd) {                        \
     name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement(), i2);   \
   }
 
 void Assembler::ris_form(Opcode op, Register r1, Condition m3, Register b4,
                          Disp d4, const Operand& i2) {
   DCHECK(is_uint12(d4));
   DCHECK(is_uint16(op));
-  DCHECK(is_uint8(i2.imm_));
+  DCHECK(is_uint8(i2.immediate()));
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
                   (static_cast<uint64_t>(r1.code())) * B36 |
                   (static_cast<uint64_t>(m3)) * B32 |
                   (static_cast<uint64_t>(b4.code())) * B28 |
                   (static_cast<uint64_t>(d4)) * B16 |
-                  (static_cast<uint64_t>(i2.imm_)) << 8 |
+                  (static_cast<uint64_t>(i2.immediate())) << 8 |
                   (static_cast<uint64_t>(op & 0x00FF));
   emit6bytes(code);
 }
 
 // S format: <insn> D2(B2)
 //    +------------------+----+-------------+
 //    |      OpCode      | B2 |     D2      |
 //    +------------------+----+-------------+
 //    0                  16   20           31
 #define S_FORM_EMIT(name, op)                                        \
@@ skipping 14 matching lines @@
 //    0        8         16   20           31
 #define SI_FORM_EMIT(name, op)                                      \
   void Assembler::name(const Operand& i2, Register b1, Disp d1) {   \
     si_form(op, i2, b1, d1);                                        \
   }                                                                 \
   void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
     name(i2, opnd.getBaseRegister(), opnd.getDisplacement());       \
   }
 
 void Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
-  emit4bytes((op & 0x00FF) << 24 | i2.imm_ * B16 | b1.code() * B12 | d1);
+  emit4bytes((op & 0x00FF) << 24 | i2.immediate() * B16 | b1.code() * B12 | d1);
 }
 
 // SIY format: <insn> D1(B1),I2
 //    +--------+---------+----+-------------+--------+--------+
 //    | OpCode |   I2    | B1 |     DL1     |  DH1   | OpCode |
 //    +--------+---------+----+-------------+--------+--------+
 //    0        8         16   20            32   36   40      47
 #define SIY_FORM_EMIT(name, op)                                     \
   void Assembler::name(const Operand& i2, Register b1, Disp d1) {   \
     siy_form(op, i2, b1, d1);                                       \
   }                                                                 \
   void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
     name(i2, opnd.getBaseRegister(), opnd.getDisplacement());       \
   }
 
 void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
   DCHECK(is_uint20(d1) || is_int20(d1));
   DCHECK(is_uint16(op));
-  DCHECK(is_uint8(i2.imm_));
+  DCHECK(is_uint8(i2.immediate()));
   uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
-                  (static_cast<uint64_t>(i2.imm_)) * B32 |
+                  (static_cast<uint64_t>(i2.immediate())) * B32 |
                   (static_cast<uint64_t>(b1.code())) * B28 |
                   (static_cast<uint64_t>(d1 & 0x0FFF)) * B16 |
                   (static_cast<uint64_t>(d1 & 0x0FF000)) >> 4 |
                   (static_cast<uint64_t>(op & 0x00FF));
   emit6bytes(code);
 }
 
 // SIL format: <insn> D1(B1),I2
 //    +------------------+----+-------------+-----------------+
 //    |     OpCode       | B1 |      D1     |        I2       |
 //    +------------------+----+-------------+-----------------+
 //    0                 16   20            32                47
 #define SIL_FORM_EMIT(name, op)                                     \
   void Assembler::name(Register b1, Disp d1, const Operand& i2) {   \
     sil_form(op, b1, d1, i2);                                       \
   }                                                                 \
   void Assembler::name(const MemOperand& opnd, const Operand& i2) { \
     name(opnd.getBaseRegister(), opnd.getDisplacement(), i2);       \
   }
 
 void Assembler::sil_form(Opcode op, Register b1, Disp d1, const Operand& i2) {
   DCHECK(is_uint12(d1));
   DCHECK(is_uint16(op));
-  DCHECK(is_uint16(i2.imm_));
+  DCHECK(is_uint16(i2.immediate()));
   uint64_t code = (static_cast<uint64_t>(op)) * B32 |
                   (static_cast<uint64_t>(b1.code())) * B28 |
                   (static_cast<uint64_t>(d1)) * B16 |
-                  (static_cast<uint64_t>(i2.imm_));
+                  (static_cast<uint64_t>(i2.immediate()));
   emit6bytes(code);
 }
 
 // RXF format: <insn> R1,R3,D2(X2,B2)
 //    +--------+----+----+----+-------------+----+---+--------+
 //    | OpCode | R3 | X2 | B2 |     D2      | R1 |///| OpCode |
 //    +--------+----+----+----+-------------+----+---+--------+
 //    0        8    12   16   20            32   36  40      47
 #define RXF_FORM_EMIT(name, op)                                            \
   void Assembler::name(Register r1, Register r3, Register b2, Register x2, \
@@ skipping 93 matching lines @@
   void Assembler::name(const MemOperand& opnd1, const MemOperand& opnd2,     \
                        Length length) {                                      \
     DCHECK(false);                                                           \
   }
 void Assembler::ss_form(Opcode op, Length l1, const Operand& i3, Register b1,
                         Disp d1, Register b2, Disp d2) {
   DCHECK(is_uint12(d2));
   DCHECK(is_uint12(d1));
   DCHECK(is_uint8(op));
   DCHECK(is_uint4(l1));
-  DCHECK(is_uint4(i3.imm_));
+  DCHECK(is_uint4(i3.immediate()));
   uint64_t code =
       (static_cast<uint64_t>(op)) * B40 | (static_cast<uint64_t>(l1)) * B36 |
-      (static_cast<uint64_t>(i3.imm_)) * B32 |
+      (static_cast<uint64_t>(i3.immediate())) * B32 |
       (static_cast<uint64_t>(b1.code())) * B28 |
       (static_cast<uint64_t>(d1)) * B16 |
       (static_cast<uint64_t>(b2.code())) * B12 | (static_cast<uint64_t>(d2));
   emit6bytes(code);
 }
 
 // SS4 format: <insn> D1(R1,B1), D2(R3,B2)
 //    +--------+----+----+----+-------------+----+------------+
 //    | OpCode | R1 | R3 | B1 |     D1      | B2 |     D2     |
 //    +--------+----+----+----+-------------+----+------------+
@@ skipping 277 matching lines @@
 
 // -------------------------------
 // Rotate and Insert Selected Bits
 // -------------------------------
 // Rotate-And-Insert-Selected-Bits
 void Assembler::risbg(Register dst, Register src, const Operand& startBit,
                       const Operand& endBit, const Operand& shiftAmt,
                       bool zeroBits) {
   // High tag the top bit of I4/EndBit to zero out any unselected bits
   if (zeroBits)
-    rie_f_form(RISBG, dst, src, startBit, Operand(endBit.imm_ | 0x80),
+    rie_f_form(RISBG, dst, src, startBit, Operand(endBit.immediate() | 0x80),
                shiftAmt);
   else
     rie_f_form(RISBG, dst, src, startBit, endBit, shiftAmt);
 }
 
 // Rotate-And-Insert-Selected-Bits
 void Assembler::risbgn(Register dst, Register src, const Operand& startBit,
                        const Operand& endBit, const Operand& shiftAmt,
                        bool zeroBits) {
   // High tag the top bit of I4/EndBit to zero out any unselected bits
   if (zeroBits)
-    rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.imm_ | 0x80),
+    rie_f_form(RISBGN, dst, src, startBit, Operand(endBit.immediate() | 0x80),
                shiftAmt);
   else
     rie_f_form(RISBGN, dst, src, startBit, endBit, shiftAmt);
 }
 
 // ---------------------------
 // Move Character Instructions
 // ---------------------------
 // Move charactor - mem to mem operation
 void Assembler::mvc(const MemOperand& opnd1, const MemOperand& opnd2,
@@ skipping 13 matching lines @@
   rie_form(AHIK, r1, r3, i2);
 }
 
 // Add Register-Register-Register (32)
 void Assembler::ark(Register r1, Register r2, Register r3) {
   rrf1_form(ARK, r1, r2, r3);
 }
 
 // Add Storage-Imm (32)
 void Assembler::asi(const MemOperand& opnd, const Operand& imm) {
-  DCHECK(is_int8(imm.imm_));
+  DCHECK(is_int8(imm.immediate()));
   DCHECK(is_int20(opnd.offset()));
-  siy_form(ASI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset());
+  siy_form(ASI, Operand(0xff & imm.immediate()), opnd.rb(),
+           0xfffff & opnd.offset());
 }
 
 // -----------------------
 // 64-bit Add Instructions
 // -----------------------
 // Add Halfword Immediate (64)
 void Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); }
 
 // Add Halfword Immediate (64)
 void Assembler::aghik(Register r1, Register r3, const Operand& i2) {
   rie_form(AGHIK, r1, r3, i2);
 }
 
 // Add Register-Register-Register (64)
 void Assembler::agrk(Register r1, Register r2, Register r3) {
   rrf1_form(AGRK, r1, r2, r3);
 }
 
 // Add Storage-Imm (64)
 void Assembler::agsi(const MemOperand& opnd, const Operand& imm) {
-  DCHECK(is_int8(imm.imm_));
+  DCHECK(is_int8(imm.immediate()));
   DCHECK(is_int20(opnd.offset()));
-  siy_form(AGSI, Operand(0xff & imm.imm_), opnd.rb(), 0xfffff & opnd.offset());
+  siy_form(AGSI, Operand(0xff & imm.immediate()), opnd.rb(),
+           0xfffff & opnd.offset());
 }
 
 // -------------------------------
 // 32-bit Add Logical Instructions
 // -------------------------------
 // Add Logical Register-Register-Register (32)
 void Assembler::alrk(Register r1, Register r2, Register r3) {
   rrf1_form(ALRK, r1, r2, r3);
 }
 
@@ skipping 697 matching lines @@
                             SKIP_ICACHE_FLUSH);
     }
 
     reloc_info_writer.Write(&rinfo);
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390