base atomicops: Drop SSE2 detection, we always require SSE2 starting in m35.

base/atomicops_internals_x86_gcc.cc

Index: base/atomicops_internals_x86_gcc.cc
diff --git a/base/atomicops_internals_x86_gcc.cc b/base/atomicops_internals_x86_gcc.cc
index a208a9889c6337650e8be6068e44b8386d4a7c6c..3f47458ad19e0e0dbfffc3bebda08ac48c3f9b66 100644
--- a/base/atomicops_internals_x86_gcc.cc
+++ b/base/atomicops_internals_x86_gcc.cc
@@ -40,7 +40,6 @@
 // default values should hopefully be pretty safe.
 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
   false,          // bug can't exist before process spawns multiple threads
-  false,          // no SSE2
 };
 
 namespace {
@@ -82,9 +81,6 @@ void AtomicOps_Internalx86CPUFeaturesInit() {
   } else {
     AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
   }
-
-  // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
-  AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
 }
 
 class AtomicOpsx86Initializer {