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Issue 2919203002: [WASM] Eliminate SIMD boolean vector types. (Closed)
Patch Set: Restore DCHECKs in AssembleMove/Swap now that we're back to 1 SIMD representation. Created 3 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 170 matching lines...) Expand 10 before | Expand all | Expand 10 after
181 V(Mips64I32x4Mul) \ 181 V(Mips64I32x4Mul) \
182 V(Mips64I32x4MaxS) \ 182 V(Mips64I32x4MaxS) \
183 V(Mips64I32x4MinS) \ 183 V(Mips64I32x4MinS) \
184 V(Mips64I32x4Eq) \ 184 V(Mips64I32x4Eq) \
185 V(Mips64I32x4Ne) \ 185 V(Mips64I32x4Ne) \
186 V(Mips64I32x4Shl) \ 186 V(Mips64I32x4Shl) \
187 V(Mips64I32x4ShrS) \ 187 V(Mips64I32x4ShrS) \
188 V(Mips64I32x4ShrU) \ 188 V(Mips64I32x4ShrU) \
189 V(Mips64I32x4MaxU) \ 189 V(Mips64I32x4MaxU) \
190 V(Mips64I32x4MinU) \ 190 V(Mips64I32x4MinU) \
191 V(Mips64S32x4Select) \
192 V(Mips64F32x4Abs) \ 191 V(Mips64F32x4Abs) \
193 V(Mips64F32x4Neg) \ 192 V(Mips64F32x4Neg) \
194 V(Mips64F32x4RecipApprox) \ 193 V(Mips64F32x4RecipApprox) \
195 V(Mips64F32x4RecipSqrtApprox) \ 194 V(Mips64F32x4RecipSqrtApprox) \
196 V(Mips64F32x4Add) \ 195 V(Mips64F32x4Add) \
197 V(Mips64F32x4Sub) \ 196 V(Mips64F32x4Sub) \
198 V(Mips64F32x4Mul) \ 197 V(Mips64F32x4Mul) \
199 V(Mips64F32x4Max) \ 198 V(Mips64F32x4Max) \
200 V(Mips64F32x4Min) \ 199 V(Mips64F32x4Min) \
201 V(Mips64F32x4Eq) \ 200 V(Mips64F32x4Eq) \
(...skipping 30 matching lines...) Expand all
232 V(Mips64I16x8MaxU) \ 231 V(Mips64I16x8MaxU) \
233 V(Mips64I16x8MinU) \ 232 V(Mips64I16x8MinU) \
234 V(Mips64I16x8GtU) \ 233 V(Mips64I16x8GtU) \
235 V(Mips64I16x8GeU) \ 234 V(Mips64I16x8GeU) \
236 V(Mips64I8x16Splat) \ 235 V(Mips64I8x16Splat) \
237 V(Mips64I8x16ExtractLane) \ 236 V(Mips64I8x16ExtractLane) \
238 V(Mips64I8x16ReplaceLane) \ 237 V(Mips64I8x16ReplaceLane) \
239 V(Mips64I8x16Neg) \ 238 V(Mips64I8x16Neg) \
240 V(Mips64I8x16Shl) \ 239 V(Mips64I8x16Shl) \
241 V(Mips64I8x16ShrS) \ 240 V(Mips64I8x16ShrS) \
242 V(Mips64S16x8Select) \
243 V(Mips64S8x16Select) \
244 V(Mips64I8x16Add) \ 241 V(Mips64I8x16Add) \
245 V(Mips64I8x16AddSaturateS) \ 242 V(Mips64I8x16AddSaturateS) \
246 V(Mips64I8x16Sub) \ 243 V(Mips64I8x16Sub) \
247 V(Mips64I8x16SubSaturateS) \ 244 V(Mips64I8x16SubSaturateS) \
248 V(Mips64I8x16Mul) \ 245 V(Mips64I8x16Mul) \
249 V(Mips64I8x16MaxS) \ 246 V(Mips64I8x16MaxS) \
250 V(Mips64I8x16MinS) \ 247 V(Mips64I8x16MinS) \
251 V(Mips64I8x16Eq) \ 248 V(Mips64I8x16Eq) \
252 V(Mips64I8x16Ne) \ 249 V(Mips64I8x16Ne) \
253 V(Mips64I8x16GtS) \ 250 V(Mips64I8x16GtS) \
254 V(Mips64I8x16GeS) \ 251 V(Mips64I8x16GeS) \
255 V(Mips64I8x16ShrU) \ 252 V(Mips64I8x16ShrU) \
256 V(Mips64I8x16AddSaturateU) \ 253 V(Mips64I8x16AddSaturateU) \
257 V(Mips64I8x16SubSaturateU) \ 254 V(Mips64I8x16SubSaturateU) \
258 V(Mips64I8x16MaxU) \ 255 V(Mips64I8x16MaxU) \
259 V(Mips64I8x16MinU) \ 256 V(Mips64I8x16MinU) \
260 V(Mips64I8x16GtU) \ 257 V(Mips64I8x16GtU) \
261 V(Mips64I8x16GeU) \ 258 V(Mips64I8x16GeU) \
262 V(Mips64S128And) \ 259 V(Mips64S128And) \
263 V(Mips64S128Or) \ 260 V(Mips64S128Or) \
264 V(Mips64S128Xor) \ 261 V(Mips64S128Xor) \
265 V(Mips64S128Not) \ 262 V(Mips64S128Not) \
263 V(Mips64S128Select) \
266 V(Mips64S1x4AnyTrue) \ 264 V(Mips64S1x4AnyTrue) \
267 V(Mips64S1x4AllTrue) \ 265 V(Mips64S1x4AllTrue) \
268 V(Mips64S1x8AnyTrue) \ 266 V(Mips64S1x8AnyTrue) \
269 V(Mips64S1x8AllTrue) \ 267 V(Mips64S1x8AllTrue) \
270 V(Mips64S1x16AnyTrue) \ 268 V(Mips64S1x16AnyTrue) \
271 V(Mips64S1x16AllTrue) \ 269 V(Mips64S1x16AllTrue) \
272 V(Mips64MsaLd) \ 270 V(Mips64MsaLd) \
273 V(Mips64MsaSt) 271 V(Mips64MsaSt)
274 272
275 // Addressing modes represent the "shape" of inputs to an instruction. 273 // Addressing modes represent the "shape" of inputs to an instruction.
(...skipping 13 matching lines...) Expand all
289 #define TARGET_ADDRESSING_MODE_LIST(V) \ 287 #define TARGET_ADDRESSING_MODE_LIST(V) \
290 V(MRI) /* [%r0 + K] */ \ 288 V(MRI) /* [%r0 + K] */ \
291 V(MRR) /* [%r0 + %r1] */ 289 V(MRR) /* [%r0 + %r1] */
292 290
293 291
294 } // namespace compiler 292 } // namespace compiler
295 } // namespace internal 293 } // namespace internal
296 } // namespace v8 294 } // namespace v8
297 295
298 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 296 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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