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Unified Diff: src/ia32/disasm-ia32.cc

Issue 2916093002: [ia32][wasm] Support AVX instructions for I32x4Splat/ReplaceLane/ExtractLane (Closed)
Patch Set: Created 3 years, 7 months ago
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Index: src/ia32/disasm-ia32.cc
diff --git a/src/ia32/disasm-ia32.cc b/src/ia32/disasm-ia32.cc
index f09d0264ef66e6ee37153ebfdb76577a7f52ff47..22eca9f4fe8042ecd2d1373a797db903a954d885 100644
--- a/src/ia32/disasm-ia32.cc
+++ b/src/ia32/disasm-ia32.cc
@@ -817,6 +817,27 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
default:
UnimplementedInstruction();
}
+ } else if (vex_66() && vex_0f3a()) {
+ int mod, regop, rm, vvvv = vex_vreg();
+ get_modrm(*current, &mod, &regop, &rm);
+ switch (opcode) {
+ case 0x16:
+ AppendToBuffer("vpextrd ");
+ current += PrintRightOperand(current);
+ AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
+ *reinterpret_cast<int8_t*>(current));
+ current++;
+ break;
+ case 0x22:
+ AppendToBuffer("vpinsrd %s,%s,", NameOfXMMRegister(regop),
+ NameOfXMMRegister(vvvv));
+ current += PrintRightOperand(current);
+ AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
+ current++;
+ break;
+ default:
+ UnimplementedInstruction();
+ }
} else if (vex_f2() && vex_0f()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, &regop, &rm);
@@ -1101,6 +1122,16 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
+ case 0x6E:
+ AppendToBuffer("vmovd %s,", NameOfXMMRegister(regop));
+ current += PrintRightOperand(current);
+ break;
+ case 0x70:
+ AppendToBuffer("vpshufd %s,", NameOfXMMRegister(regop));
+ current += PrintRightXMMOperand(current);
+ AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
+ current++;
+ break;
case 0x71:
AppendToBuffer("vps%sw %s,%s", sf_str[regop / 2],
NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
@@ -1113,6 +1144,11 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
current++;
AppendToBuffer(",%u", *current++);
break;
+ case 0x7E:
+ AppendToBuffer("vmovd ");
+ current += PrintRightOperand(current);
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
+ break;
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, opcode) \
case 0x##opcode: { \
AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop), \
@@ -1850,13 +1886,12 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
} else if (*data == 0x16) {
data++;
int mod, regop, rm;
- get_modrm(*data, &mod, &rm, &regop);
- int8_t imm8 = static_cast<int8_t>(data[1]);
- AppendToBuffer("pextrd %s,%s,%d",
- NameOfCPURegister(regop),
- NameOfXMMRegister(rm),
- static_cast<int>(imm8));
- data += 2;
+ get_modrm(*data, &mod, &regop, &rm);
+ AppendToBuffer("pextrd ");
+ data += PrintRightOperand(data);
+ AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
+ *reinterpret_cast<int8_t*>(data));
+ data++;
} else if (*data == 0x17) {
data++;
int mod, regop, rm;
@@ -1871,12 +1906,10 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
- int8_t imm8 = static_cast<int8_t>(data[1]);
- AppendToBuffer("pinsrd %s,%s,%d",
- NameOfXMMRegister(regop),
- NameOfCPURegister(rm),
- static_cast<int>(imm8));
- data += 2;
+ AppendToBuffer("pinsrd %s,", NameOfXMMRegister(regop));
+ data += PrintRightOperand(data);
+ AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
+ data++;
} else {
UnimplementedInstruction();
}
@@ -1942,12 +1975,10 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
- int8_t imm8 = static_cast<int8_t>(data[1]);
- AppendToBuffer("pshufd %s,%s,%d",
- NameOfXMMRegister(regop),
- NameOfXMMRegister(rm),
- static_cast<int>(imm8));
- data += 2;
+ AppendToBuffer("pshufd %s,", NameOfXMMRegister(regop));
+ data += PrintRightXMMOperand(data);
+ AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
+ data++;
} else if (*data == 0x90) {
data++;
AppendToBuffer("nop"); // 2 byte nop.
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