Chromium Code Reviews| OLD | NEW |
|---|---|
| 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ | 5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ |
| 6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ | 6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ |
| 7 | 7 |
| 8 #ifndef RUNTIME_VM_ASSEMBLER_H_ | 8 #ifndef RUNTIME_VM_ASSEMBLER_H_ |
| 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. | 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. |
| 10 #endif | 10 #endif |
| (...skipping 724 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 735 (a.type() == Address::PairPreIndex)); | 735 (a.type() == Address::PairPreIndex)); |
| 736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); | 736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); |
| 737 } | 737 } |
| 738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { | 738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { |
| 739 ASSERT((a.type() == Address::PairOffset) || | 739 ASSERT((a.type() == Address::PairOffset) || |
| 740 (a.type() == Address::PairPostIndex) || | 740 (a.type() == Address::PairPostIndex) || |
| 741 (a.type() == Address::PairPreIndex)); | 741 (a.type() == Address::PairPreIndex)); |
| 742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); | 742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); |
| 743 } | 743 } |
| 744 | 744 |
| 745 void ldxr(Register rt, Register rn) { | 745 void ldxr(Register rt, Register rn, OperandSize size = kDoubleWord) { |
|
rmacnak
2017/06/19 18:12:21
Please copy the ldxr/stxr tests in assembler_arm64
erikcorry
2017/06/21 12:12:12
Done.
| |
| 746 // rt = value | 746 // rt = value |
| 747 // rn = address | 747 // rn = address |
| 748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord); | 748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, size); |
| 749 } | 749 } |
| 750 void stxr(Register rs, Register rt, Register rn) { | 750 void stxr(Register rs, |
| 751 Register rt, | |
| 752 Register rn, | |
| 753 OperandSize size = kDoubleWord) { | |
| 751 // rs = status (1 = failure, 0 = success) | 754 // rs = status (1 = failure, 0 = success) |
| 752 // rt = value | 755 // rt = value |
| 753 // rn = address | 756 // rn = address |
| 754 EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord); | 757 EmitLoadStoreExclusive(STXR, rs, rn, rt, size); |
| 755 } | 758 } |
| 756 void clrex() { | 759 void clrex() { |
| 757 const int32_t encoding = static_cast<int32_t>(CLREX); | 760 const int32_t encoding = static_cast<int32_t>(CLREX); |
| 758 Emit(encoding); | 761 Emit(encoding); |
| 759 } | 762 } |
| 760 | 763 |
| 761 // Conditional select. | 764 // Conditional select. |
| 762 void csel(Register rd, Register rn, Register rm, Condition cond) { | 765 void csel(Register rd, Register rn, Register rm, Condition cond) { |
| 763 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); | 766 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); |
| 764 } | 767 } |
| (...skipping 917 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 1682 (static_cast<int32_t>(hw_idx) << kHWShift) | | 1685 (static_cast<int32_t>(hw_idx) << kHWShift) | |
| 1683 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); | 1686 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); |
| 1684 Emit(encoding); | 1687 Emit(encoding); |
| 1685 } | 1688 } |
| 1686 | 1689 |
| 1687 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, | 1690 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, |
| 1688 Register rs, | 1691 Register rs, |
| 1689 Register rn, | 1692 Register rn, |
| 1690 Register rt, | 1693 Register rt, |
| 1691 OperandSize sz = kDoubleWord) { | 1694 OperandSize sz = kDoubleWord) { |
| 1692 ASSERT(sz == kDoubleWord); | 1695 ASSERT(sz == kDoubleWord || sz == kWord); |
| 1693 const int32_t size = B31 | B30; | 1696 const int32_t size = B31 | (sz == kDoubleWord ? B30 : 0); |
| 1694 | 1697 |
| 1695 ASSERT((rs != kNoRegister) && (rs != ZR)); | 1698 ASSERT((rs != kNoRegister) && (rs != ZR)); |
| 1696 ASSERT((rn != kNoRegister) && (rn != ZR)); | 1699 ASSERT((rn != kNoRegister) && (rn != ZR)); |
| 1697 ASSERT((rt != kNoRegister) && (rt != ZR)); | 1700 ASSERT((rt != kNoRegister) && (rt != ZR)); |
| 1698 | 1701 |
| 1699 const int32_t encoding = | 1702 const int32_t encoding = |
| 1700 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | | 1703 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | |
| 1701 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | | 1704 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | |
| 1702 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); | 1705 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); |
| 1703 | 1706 |
| (...skipping 218 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 1922 Register value, | 1925 Register value, |
| 1923 Label* no_update); | 1926 Label* no_update); |
| 1924 | 1927 |
| 1925 DISALLOW_ALLOCATION(); | 1928 DISALLOW_ALLOCATION(); |
| 1926 DISALLOW_COPY_AND_ASSIGN(Assembler); | 1929 DISALLOW_COPY_AND_ASSIGN(Assembler); |
| 1927 }; | 1930 }; |
| 1928 | 1931 |
| 1929 } // namespace dart | 1932 } // namespace dart |
| 1930 | 1933 |
| 1931 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ | 1934 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ |
| OLD | NEW |