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Side by Side Diff: src/compiler/mips64/instruction-selector-mips64.cc

Issue 2910533003: MIPS[64]: SIMD Visitors macro-ization (Closed)
Patch Set: Rebase Created 3 years, 6 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
(...skipping 2683 matching lines...) Expand 10 before | Expand all | Expand 10 after
2694 void InstructionSelector::VisitAtomicXor(Node* node) { UNIMPLEMENTED(); } 2694 void InstructionSelector::VisitAtomicXor(Node* node) { UNIMPLEMENTED(); }
2695 2695
2696 void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) { 2696 void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
2697 UNREACHABLE(); 2697 UNREACHABLE();
2698 } 2698 }
2699 2699
2700 void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { 2700 void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
2701 UNREACHABLE(); 2701 UNREACHABLE();
2702 } 2702 }
2703 2703
2704 void InstructionSelector::VisitI32x4Splat(Node* node) { 2704 #define SIMD_TYPE_LIST(V) \
2705 VisitRR(this, kMips64I32x4Splat, node); 2705 V(F32x4) \
2706 } 2706 V(I32x4) \
2707 V(I16x8) \
2708 V(I8x16)
2707 2709
2708 void InstructionSelector::VisitI32x4ExtractLane(Node* node) { 2710 #define SIMD_FORMAT_LIST(V) \
2709 VisitRRI(this, kMips64I32x4ExtractLane, node); 2711 V(32x4) \
2710 } 2712 V(16x8) \
2713 V(8x16)
2711 2714
2712 void InstructionSelector::VisitI32x4ReplaceLane(Node* node) { 2715 #define SIMD_ZERO_OP_LIST(V) \
2713 VisitRRIR(this, kMips64I32x4ReplaceLane, node); 2716 V(S128Zero) \
2714 } 2717 V(S1x4Zero) \
2718 V(S1x8Zero) \
2719 V(S1x16Zero)
2715 2720
2716 void InstructionSelector::VisitI32x4Add(Node* node) { 2721 #define SIMD_UNOP_LIST(V) \
2717 VisitRRR(this, kMips64I32x4Add, node); 2722 V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
2718 } 2723 V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
2724 V(F32x4Abs, kMips64F32x4Abs) \
2725 V(F32x4Neg, kMips64F32x4Neg) \
2726 V(F32x4RecipApprox, kMips64F32x4RecipApprox) \
2727 V(F32x4RecipSqrtApprox, kMips64F32x4RecipSqrtApprox) \
2728 V(I32x4SConvertF32x4, kMips64I32x4SConvertF32x4) \
2729 V(I32x4UConvertF32x4, kMips64I32x4UConvertF32x4) \
2730 V(I32x4Neg, kMips64I32x4Neg) \
2731 V(I16x8Neg, kMips64I16x8Neg) \
2732 V(I8x16Neg, kMips64I8x16Neg) \
2733 V(S128Not, kMips64S128Not) \
2734 V(S1x4Not, kMips64S128Not) \
2735 V(S1x4AnyTrue, kMips64S1x4AnyTrue) \
2736 V(S1x4AllTrue, kMips64S1x4AllTrue) \
2737 V(S1x8Not, kMips64S128Not) \
2738 V(S1x8AnyTrue, kMips64S1x8AnyTrue) \
2739 V(S1x8AllTrue, kMips64S1x8AllTrue) \
2740 V(S1x16Not, kMips64S128Not) \
2741 V(S1x16AnyTrue, kMips64S1x16AnyTrue) \
2742 V(S1x16AllTrue, kMips64S1x16AllTrue)
2719 2743
2720 void InstructionSelector::VisitI32x4Sub(Node* node) { 2744 #define SIMD_SHIFT_OP_LIST(V) \
2721 VisitRRR(this, kMips64I32x4Sub, node); 2745 V(I32x4Shl) \
2722 } 2746 V(I32x4ShrS) \
2747 V(I32x4ShrU) \
2748 V(I16x8Shl) \
2749 V(I16x8ShrS) \
2750 V(I16x8ShrU) \
2751 V(I8x16Shl) \
2752 V(I8x16ShrS) \
2753 V(I8x16ShrU)
2723 2754
2724 void InstructionSelector::VisitS128Zero(Node* node) { 2755 #define SIMD_BINOP_LIST(V) \
2725 Mips64OperandGenerator g(this); 2756 V(F32x4Add, kMips64F32x4Add) \
2726 Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); 2757 V(F32x4Sub, kMips64F32x4Sub) \
2727 } 2758 V(F32x4Mul, kMips64F32x4Mul) \
2759 V(F32x4Max, kMips64F32x4Max) \
2760 V(F32x4Min, kMips64F32x4Min) \
2761 V(F32x4Eq, kMips64F32x4Eq) \
2762 V(F32x4Ne, kMips64F32x4Ne) \
2763 V(F32x4Lt, kMips64F32x4Lt) \
2764 V(F32x4Le, kMips64F32x4Le) \
2765 V(I32x4Add, kMips64I32x4Add) \
2766 V(I32x4Sub, kMips64I32x4Sub) \
2767 V(I32x4Mul, kMips64I32x4Mul) \
2768 V(I32x4MaxS, kMips64I32x4MaxS) \
2769 V(I32x4MinS, kMips64I32x4MinS) \
2770 V(I32x4MaxU, kMips64I32x4MaxU) \
2771 V(I32x4MinU, kMips64I32x4MinU) \
2772 V(I32x4Eq, kMips64I32x4Eq) \
2773 V(I32x4Ne, kMips64I32x4Ne) \
2774 V(I32x4GtS, kMips64I32x4GtS) \
2775 V(I32x4GeS, kMips64I32x4GeS) \
2776 V(I32x4GtU, kMips64I32x4GtU) \
2777 V(I32x4GeU, kMips64I32x4GeU) \
2778 V(I16x8Add, kMips64I16x8Add) \
2779 V(I16x8AddSaturateS, kMips64I16x8AddSaturateS) \
2780 V(I16x8AddSaturateU, kMips64I16x8AddSaturateU) \
2781 V(I16x8Sub, kMips64I16x8Sub) \
2782 V(I16x8SubSaturateS, kMips64I16x8SubSaturateS) \
2783 V(I16x8SubSaturateU, kMips64I16x8SubSaturateU) \
2784 V(I16x8Mul, kMips64I16x8Mul) \
2785 V(I16x8MaxS, kMips64I16x8MaxS) \
2786 V(I16x8MinS, kMips64I16x8MinS) \
2787 V(I16x8MaxU, kMips64I16x8MaxU) \
2788 V(I16x8MinU, kMips64I16x8MinU) \
2789 V(I16x8Eq, kMips64I16x8Eq) \
2790 V(I16x8Ne, kMips64I16x8Ne) \
2791 V(I16x8GtS, kMips64I16x8GtS) \
2792 V(I16x8GeS, kMips64I16x8GeS) \
2793 V(I16x8GtU, kMips64I16x8GtU) \
2794 V(I16x8GeU, kMips64I16x8GeU) \
2795 V(I8x16Add, kMips64I8x16Add) \
2796 V(I8x16AddSaturateS, kMips64I8x16AddSaturateS) \
2797 V(I8x16AddSaturateU, kMips64I8x16AddSaturateU) \
2798 V(I8x16Sub, kMips64I8x16Sub) \
2799 V(I8x16SubSaturateS, kMips64I8x16SubSaturateS) \
2800 V(I8x16SubSaturateU, kMips64I8x16SubSaturateU) \
2801 V(I8x16Mul, kMips64I8x16Mul) \
2802 V(I8x16MaxS, kMips64I8x16MaxS) \
2803 V(I8x16MinS, kMips64I8x16MinS) \
2804 V(I8x16MaxU, kMips64I8x16MaxU) \
2805 V(I8x16MinU, kMips64I8x16MinU) \
2806 V(I8x16Eq, kMips64I8x16Eq) \
2807 V(I8x16Ne, kMips64I8x16Ne) \
2808 V(I8x16GtS, kMips64I8x16GtS) \
2809 V(I8x16GeS, kMips64I8x16GeS) \
2810 V(I8x16GtU, kMips64I8x16GtU) \
2811 V(I8x16GeU, kMips64I8x16GeU) \
2812 V(S128And, kMips64S128And) \
2813 V(S128Or, kMips64S128Or) \
2814 V(S128Xor, kMips64S128Xor) \
2815 V(S1x4And, kMips64S128And) \
2816 V(S1x4Or, kMips64S128Or) \
2817 V(S1x4Xor, kMips64S128Xor) \
2818 V(S1x8And, kMips64S128And) \
2819 V(S1x8Or, kMips64S128Or) \
2820 V(S1x8Xor, kMips64S128Xor) \
2821 V(S1x16And, kMips64S128And) \
2822 V(S1x16Or, kMips64S128Or) \
2823 V(S1x16Xor, kMips64S128Xor)
2728 2824
2729 void InstructionSelector::VisitS1x4Zero(Node* node) { 2825 #define SIMD_VISIT_ZERO_OP(Name) \
2730 Mips64OperandGenerator g(this); 2826 void InstructionSelector::Visit##Name(Node* node) { \
2731 Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); 2827 Mips64OperandGenerator g(this); \
2732 } 2828 Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); \
2829 }
2830 SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
2831 #undef SIMD_VISIT_ZERO_OP
2733 2832
2734 void InstructionSelector::VisitS1x8Zero(Node* node) { 2833 #define SIMD_VISIT_SPLAT(Type) \
2735 Mips64OperandGenerator g(this); 2834 void InstructionSelector::Visit##Type##Splat(Node* node) { \
2736 Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); 2835 VisitRR(this, kMips64##Type##Splat, node); \
2737 } 2836 }
2837 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
2838 #undef SIMD_VISIT_SPLAT
2738 2839
2739 void InstructionSelector::VisitS1x16Zero(Node* node) { 2840 #define SIMD_VISIT_EXTRACT_LANE(Type) \
2740 Mips64OperandGenerator g(this); 2841 void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
2741 Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); 2842 VisitRRI(this, kMips64##Type##ExtractLane, node); \
2742 } 2843 }
2844 SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
2845 #undef SIMD_VISIT_EXTRACT_LANE
2743 2846
2744 void InstructionSelector::VisitF32x4Splat(Node* node) { 2847 #define SIMD_VISIT_REPLACE_LANE(Type) \
2745 VisitRR(this, kMips64F32x4Splat, node); 2848 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2746 } 2849 VisitRRIR(this, kMips64##Type##ReplaceLane, node); \
2850 }
2851 SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
2852 #undef SIMD_VISIT_REPLACE_LANE
2747 2853
2748 void InstructionSelector::VisitF32x4ExtractLane(Node* node) { 2854 #define SIMD_VISIT_UNOP(Name, instruction) \
2749 VisitRRI(this, kMips64F32x4ExtractLane, node); 2855 void InstructionSelector::Visit##Name(Node* node) { \
2750 } 2856 VisitRR(this, instruction, node); \
2857 }
2858 SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
2859 #undef SIMD_VISIT_UNOP
2751 2860
2752 void InstructionSelector::VisitF32x4ReplaceLane(Node* node) { 2861 #define SIMD_VISIT_SHIFT_OP(Name) \
2753 VisitRRIR(this, kMips64F32x4ReplaceLane, node); 2862 void InstructionSelector::Visit##Name(Node* node) { \
2754 } 2863 VisitRRI(this, kMips64##Name, node); \
2864 }
2865 SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
2866 #undef SIMD_VISIT_SHIFT_OP
2755 2867
2756 void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) { 2868 #define SIMD_VISIT_BINOP(Name, instruction) \
2757 VisitRR(this, kMips64F32x4SConvertI32x4, node); 2869 void InstructionSelector::Visit##Name(Node* node) { \
2758 } 2870 VisitRRR(this, instruction, node); \
2871 }
2872 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
2873 #undef SIMD_VISIT_BINOP
2759 2874
2760 void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) { 2875 #define SIMD_VISIT_SELECT_OP(format) \
2761 VisitRR(this, kMips64F32x4UConvertI32x4, node); 2876 void InstructionSelector::VisitS##format##Select(Node* node) { \
2762 } 2877 VisitRRRR(this, kMips64S##format##Select, node); \
2763 2878 }
2764 void InstructionSelector::VisitI32x4Mul(Node* node) { 2879 SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
2765 VisitRRR(this, kMips64I32x4Mul, node); 2880 #undef SIMD_VISIT_SELECT_OP
2766 }
2767
2768 void InstructionSelector::VisitI32x4MaxS(Node* node) {
2769 VisitRRR(this, kMips64I32x4MaxS, node);
2770 }
2771
2772 void InstructionSelector::VisitI32x4MinS(Node* node) {
2773 VisitRRR(this, kMips64I32x4MinS, node);
2774 }
2775
2776 void InstructionSelector::VisitI32x4Eq(Node* node) {
2777 VisitRRR(this, kMips64I32x4Eq, node);
2778 }
2779
2780 void InstructionSelector::VisitI32x4Ne(Node* node) {
2781 VisitRRR(this, kMips64I32x4Ne, node);
2782 }
2783
2784 void InstructionSelector::VisitI32x4Shl(Node* node) {
2785 VisitRRI(this, kMips64I32x4Shl, node);
2786 }
2787
2788 void InstructionSelector::VisitI32x4ShrS(Node* node) {
2789 VisitRRI(this, kMips64I32x4ShrS, node);
2790 }
2791
2792 void InstructionSelector::VisitI32x4ShrU(Node* node) {
2793 VisitRRI(this, kMips64I32x4ShrU, node);
2794 }
2795
2796 void InstructionSelector::VisitI32x4MaxU(Node* node) {
2797 VisitRRR(this, kMips64I32x4MaxU, node);
2798 }
2799
2800 void InstructionSelector::VisitI32x4MinU(Node* node) {
2801 VisitRRR(this, kMips64I32x4MinU, node);
2802 }
2803
2804 void InstructionSelector::VisitS32x4Select(Node* node) {
2805 VisitRRRR(this, kMips64S32x4Select, node);
2806 }
2807
2808 void InstructionSelector::VisitF32x4Abs(Node* node) {
2809 VisitRR(this, kMips64F32x4Abs, node);
2810 }
2811
2812 void InstructionSelector::VisitF32x4Neg(Node* node) {
2813 VisitRR(this, kMips64F32x4Neg, node);
2814 }
2815
2816 void InstructionSelector::VisitF32x4RecipApprox(Node* node) {
2817 VisitRR(this, kMips64F32x4RecipApprox, node);
2818 }
2819
2820 void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
2821 VisitRR(this, kMips64F32x4RecipSqrtApprox, node);
2822 }
2823
2824 void InstructionSelector::VisitF32x4Add(Node* node) {
2825 VisitRRR(this, kMips64F32x4Add, node);
2826 }
2827
2828 void InstructionSelector::VisitF32x4Sub(Node* node) {
2829 VisitRRR(this, kMips64F32x4Sub, node);
2830 }
2831
2832 void InstructionSelector::VisitF32x4Mul(Node* node) {
2833 VisitRRR(this, kMips64F32x4Mul, node);
2834 }
2835
2836 void InstructionSelector::VisitF32x4Max(Node* node) {
2837 VisitRRR(this, kMips64F32x4Max, node);
2838 }
2839
2840 void InstructionSelector::VisitF32x4Min(Node* node) {
2841 VisitRRR(this, kMips64F32x4Min, node);
2842 }
2843
2844 void InstructionSelector::VisitF32x4Eq(Node* node) {
2845 VisitRRR(this, kMips64F32x4Eq, node);
2846 }
2847
2848 void InstructionSelector::VisitF32x4Ne(Node* node) {
2849 VisitRRR(this, kMips64F32x4Ne, node);
2850 }
2851
2852 void InstructionSelector::VisitF32x4Lt(Node* node) {
2853 VisitRRR(this, kMips64F32x4Lt, node);
2854 }
2855
2856 void InstructionSelector::VisitF32x4Le(Node* node) {
2857 VisitRRR(this, kMips64F32x4Le, node);
2858 }
2859
2860 void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
2861 VisitRR(this, kMips64I32x4SConvertF32x4, node);
2862 }
2863
2864 void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
2865 VisitRR(this, kMips64I32x4UConvertF32x4, node);
2866 }
2867
2868 void InstructionSelector::VisitI32x4Neg(Node* node) {
2869 VisitRR(this, kMips64I32x4Neg, node);
2870 }
2871
2872 void InstructionSelector::VisitI32x4GtS(Node* node) {
2873 VisitRRR(this, kMips64I32x4GtS, node);
2874 }
2875
2876 void InstructionSelector::VisitI32x4GeS(Node* node) {
2877 VisitRRR(this, kMips64I32x4GeS, node);
2878 }
2879
2880 void InstructionSelector::VisitI32x4GtU(Node* node) {
2881 VisitRRR(this, kMips64I32x4GtU, node);
2882 }
2883
2884 void InstructionSelector::VisitI32x4GeU(Node* node) {
2885 VisitRRR(this, kMips64I32x4GeU, node);
2886 }
2887
2888 void InstructionSelector::VisitI16x8Splat(Node* node) {
2889 VisitRR(this, kMips64I16x8Splat, node);
2890 }
2891
2892 void InstructionSelector::VisitI16x8ExtractLane(Node* node) {
2893 VisitRRI(this, kMips64I16x8ExtractLane, node);
2894 }
2895
2896 void InstructionSelector::VisitI16x8ReplaceLane(Node* node) {
2897 VisitRRIR(this, kMips64I16x8ReplaceLane, node);
2898 }
2899
2900 void InstructionSelector::VisitI16x8Neg(Node* node) {
2901 VisitRR(this, kMips64I16x8Neg, node);
2902 }
2903
2904 void InstructionSelector::VisitI16x8Shl(Node* node) {
2905 VisitRRI(this, kMips64I16x8Shl, node);
2906 }
2907
2908 void InstructionSelector::VisitI16x8ShrS(Node* node) {
2909 VisitRRI(this, kMips64I16x8ShrS, node);
2910 }
2911
2912 void InstructionSelector::VisitI16x8ShrU(Node* node) {
2913 VisitRRI(this, kMips64I16x8ShrU, node);
2914 }
2915
2916 void InstructionSelector::VisitI16x8Add(Node* node) {
2917 VisitRRR(this, kMips64I16x8Add, node);
2918 }
2919
2920 void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
2921 VisitRRR(this, kMips64I16x8AddSaturateS, node);
2922 }
2923
2924 void InstructionSelector::VisitI16x8Sub(Node* node) {
2925 VisitRRR(this, kMips64I16x8Sub, node);
2926 }
2927
2928 void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
2929 VisitRRR(this, kMips64I16x8SubSaturateS, node);
2930 }
2931
2932 void InstructionSelector::VisitI16x8Mul(Node* node) {
2933 VisitRRR(this, kMips64I16x8Mul, node);
2934 }
2935
2936 void InstructionSelector::VisitI16x8MaxS(Node* node) {
2937 VisitRRR(this, kMips64I16x8MaxS, node);
2938 }
2939
2940 void InstructionSelector::VisitI16x8MinS(Node* node) {
2941 VisitRRR(this, kMips64I16x8MinS, node);
2942 }
2943
2944 void InstructionSelector::VisitI16x8Eq(Node* node) {
2945 VisitRRR(this, kMips64I16x8Eq, node);
2946 }
2947
2948 void InstructionSelector::VisitI16x8Ne(Node* node) {
2949 VisitRRR(this, kMips64I16x8Ne, node);
2950 }
2951
2952 void InstructionSelector::VisitI16x8GtS(Node* node) {
2953 VisitRRR(this, kMips64I16x8GtS, node);
2954 }
2955
2956 void InstructionSelector::VisitI16x8GeS(Node* node) {
2957 VisitRRR(this, kMips64I16x8GeS, node);
2958 }
2959
2960 void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
2961 VisitRRR(this, kMips64I16x8AddSaturateU, node);
2962 }
2963
2964 void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
2965 VisitRRR(this, kMips64I16x8SubSaturateU, node);
2966 }
2967
2968 void InstructionSelector::VisitI16x8MaxU(Node* node) {
2969 VisitRRR(this, kMips64I16x8MaxU, node);
2970 }
2971
2972 void InstructionSelector::VisitI16x8MinU(Node* node) {
2973 VisitRRR(this, kMips64I16x8MinU, node);
2974 }
2975
2976 void InstructionSelector::VisitI16x8GtU(Node* node) {
2977 VisitRRR(this, kMips64I16x8GtU, node);
2978 }
2979
2980 void InstructionSelector::VisitI16x8GeU(Node* node) {
2981 VisitRRR(this, kMips64I16x8GeU, node);
2982 }
2983
2984 void InstructionSelector::VisitI8x16Splat(Node* node) {
2985 VisitRR(this, kMips64I8x16Splat, node);
2986 }
2987
2988 void InstructionSelector::VisitI8x16ExtractLane(Node* node) {
2989 VisitRRI(this, kMips64I8x16ExtractLane, node);
2990 }
2991
2992 void InstructionSelector::VisitI8x16ReplaceLane(Node* node) {
2993 VisitRRIR(this, kMips64I8x16ReplaceLane, node);
2994 }
2995
2996 void InstructionSelector::VisitI8x16Neg(Node* node) {
2997 VisitRR(this, kMips64I8x16Neg, node);
2998 }
2999
3000 void InstructionSelector::VisitI8x16Shl(Node* node) {
3001 VisitRRI(this, kMips64I8x16Shl, node);
3002 }
3003
3004 void InstructionSelector::VisitI8x16ShrS(Node* node) {
3005 VisitRRI(this, kMips64I8x16ShrS, node);
3006 }
3007
3008 void InstructionSelector::VisitS16x8Select(Node* node) {
3009 VisitRRRR(this, kMips64S16x8Select, node);
3010 }
3011
3012 void InstructionSelector::VisitS8x16Select(Node* node) {
3013 VisitRRRR(this, kMips64S8x16Select, node);
3014 }
3015
3016 void InstructionSelector::VisitI8x16Add(Node* node) {
3017 VisitRRR(this, kMips64I8x16Add, node);
3018 }
3019
3020 void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
3021 VisitRRR(this, kMips64I8x16AddSaturateS, node);
3022 }
3023
3024 void InstructionSelector::VisitI8x16Sub(Node* node) {
3025 VisitRRR(this, kMips64I8x16Sub, node);
3026 }
3027
3028 void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
3029 VisitRRR(this, kMips64I8x16SubSaturateS, node);
3030 }
3031
3032 void InstructionSelector::VisitI8x16Mul(Node* node) {
3033 VisitRRR(this, kMips64I8x16Mul, node);
3034 }
3035
3036 void InstructionSelector::VisitI8x16MaxS(Node* node) {
3037 VisitRRR(this, kMips64I8x16MaxS, node);
3038 }
3039
3040 void InstructionSelector::VisitI8x16MinS(Node* node) {
3041 VisitRRR(this, kMips64I8x16MinS, node);
3042 }
3043
3044 void InstructionSelector::VisitI8x16Eq(Node* node) {
3045 VisitRRR(this, kMips64I8x16Eq, node);
3046 }
3047
3048 void InstructionSelector::VisitI8x16Ne(Node* node) {
3049 VisitRRR(this, kMips64I8x16Ne, node);
3050 }
3051
3052 void InstructionSelector::VisitI8x16GtS(Node* node) {
3053 VisitRRR(this, kMips64I8x16GtS, node);
3054 }
3055
3056 void InstructionSelector::VisitI8x16GeS(Node* node) {
3057 VisitRRR(this, kMips64I8x16GeS, node);
3058 }
3059
3060 void InstructionSelector::VisitI8x16ShrU(Node* node) {
3061 VisitRRI(this, kMips64I8x16ShrU, node);
3062 }
3063
3064 void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
3065 VisitRRR(this, kMips64I8x16AddSaturateU, node);
3066 }
3067
3068 void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
3069 VisitRRR(this, kMips64I8x16SubSaturateU, node);
3070 }
3071
3072 void InstructionSelector::VisitI8x16MaxU(Node* node) {
3073 VisitRRR(this, kMips64I8x16MaxU, node);
3074 }
3075
3076 void InstructionSelector::VisitI8x16MinU(Node* node) {
3077 VisitRRR(this, kMips64I8x16MinU, node);
3078 }
3079
3080 void InstructionSelector::VisitI8x16GtU(Node* node) {
3081 VisitRRR(this, kMips64I8x16GtU, node);
3082 }
3083
3084 void InstructionSelector::VisitI8x16GeU(Node* node) {
3085 VisitRRR(this, kMips64I8x16GeU, node);
3086 }
3087
3088 void InstructionSelector::VisitS128And(Node* node) {
3089 VisitRRR(this, kMips64S128And, node);
3090 }
3091
3092 void InstructionSelector::VisitS128Or(Node* node) {
3093 VisitRRR(this, kMips64S128Or, node);
3094 }
3095
3096 void InstructionSelector::VisitS128Xor(Node* node) {
3097 VisitRRR(this, kMips64S128Xor, node);
3098 }
3099
3100 void InstructionSelector::VisitS128Not(Node* node) {
3101 VisitRR(this, kMips64S128Not, node);
3102 }
3103
3104 void InstructionSelector::VisitS1x4And(Node* node) {
3105 VisitRRR(this, kMips64S128And, node);
3106 }
3107
3108 void InstructionSelector::VisitS1x4Or(Node* node) {
3109 VisitRRR(this, kMips64S128Or, node);
3110 }
3111
3112 void InstructionSelector::VisitS1x4Xor(Node* node) {
3113 VisitRRR(this, kMips64S128Xor, node);
3114 }
3115
3116 void InstructionSelector::VisitS1x4Not(Node* node) {
3117 VisitRR(this, kMips64S128Not, node);
3118 }
3119
3120 void InstructionSelector::VisitS1x4AnyTrue(Node* node) {
3121 VisitRR(this, kMips64S1x4AnyTrue, node);
3122 }
3123
3124 void InstructionSelector::VisitS1x4AllTrue(Node* node) {
3125 VisitRR(this, kMips64S1x4AllTrue, node);
3126 }
3127
3128 void InstructionSelector::VisitS1x8And(Node* node) {
3129 VisitRRR(this, kMips64S128And, node);
3130 }
3131
3132 void InstructionSelector::VisitS1x8Or(Node* node) {
3133 VisitRRR(this, kMips64S128Or, node);
3134 }
3135
3136 void InstructionSelector::VisitS1x8Xor(Node* node) {
3137 VisitRRR(this, kMips64S128Xor, node);
3138 }
3139
3140 void InstructionSelector::VisitS1x8Not(Node* node) {
3141 VisitRR(this, kMips64S128Not, node);
3142 }
3143
3144 void InstructionSelector::VisitS1x8AnyTrue(Node* node) {
3145 VisitRR(this, kMips64S1x8AnyTrue, node);
3146 }
3147
3148 void InstructionSelector::VisitS1x8AllTrue(Node* node) {
3149 VisitRR(this, kMips64S1x8AllTrue, node);
3150 }
3151
3152 void InstructionSelector::VisitS1x16And(Node* node) {
3153 VisitRRR(this, kMips64S128And, node);
3154 }
3155
3156 void InstructionSelector::VisitS1x16Or(Node* node) {
3157 VisitRRR(this, kMips64S128Or, node);
3158 }
3159
3160 void InstructionSelector::VisitS1x16Xor(Node* node) {
3161 VisitRRR(this, kMips64S128Xor, node);
3162 }
3163
3164 void InstructionSelector::VisitS1x16Not(Node* node) {
3165 VisitRR(this, kMips64S128Not, node);
3166 }
3167
3168 void InstructionSelector::VisitS1x16AnyTrue(Node* node) {
3169 VisitRR(this, kMips64S1x16AnyTrue, node);
3170 }
3171
3172 void InstructionSelector::VisitS1x16AllTrue(Node* node) {
3173 VisitRR(this, kMips64S1x16AllTrue, node);
3174 }
3175 2881
3176 // static 2882 // static
3177 MachineOperatorBuilder::Flags 2883 MachineOperatorBuilder::Flags
3178 InstructionSelector::SupportedMachineOperatorFlags() { 2884 InstructionSelector::SupportedMachineOperatorFlags() {
3179 MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags; 2885 MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags;
3180 return flags | MachineOperatorBuilder::kWord32Ctz | 2886 return flags | MachineOperatorBuilder::kWord32Ctz |
3181 MachineOperatorBuilder::kWord64Ctz | 2887 MachineOperatorBuilder::kWord64Ctz |
3182 MachineOperatorBuilder::kWord32Popcnt | 2888 MachineOperatorBuilder::kWord32Popcnt |
3183 MachineOperatorBuilder::kWord64Popcnt | 2889 MachineOperatorBuilder::kWord64Popcnt |
3184 MachineOperatorBuilder::kWord32ShiftIsSafe | 2890 MachineOperatorBuilder::kWord32ShiftIsSafe |
(...skipping 20 matching lines...) Expand all
3205 } else { 2911 } else {
3206 DCHECK(kArchVariant == kMips64r2); 2912 DCHECK(kArchVariant == kMips64r2);
3207 return MachineOperatorBuilder::AlignmentRequirements:: 2913 return MachineOperatorBuilder::AlignmentRequirements::
3208 NoUnalignedAccessSupport(); 2914 NoUnalignedAccessSupport();
3209 } 2915 }
3210 } 2916 }
3211 2917
3212 } // namespace compiler 2918 } // namespace compiler
3213 } // namespace internal 2919 } // namespace internal
3214 } // namespace v8 2920 } // namespace v8
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