MIPS64: Add optimizations to li and Dsubu macro.

test/cctest/test-assembler-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 5053 matching lines @@
   if (num_instr > 0) {
     CHECK_EQ(assm.InstructionsGeneratedSince(&code_start), num_instr);
   }
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(isolate, &desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
+#ifdef OBJECT_PRINT
+  code->Print(std::cout);
+#endif
   F2 f = FUNCTION_CAST<F2>(code->entry());
 
   uint64_t res = reinterpret_cast<uint64_t>(
       CALL_GENERATED_CODE(isolate, f, 0, 0, 0, 0, 0));
 
   return res;
 }
 
 
 TEST(li_macro) {
@@ skipping 32 matching lines @@
       // r2 - daddiu + dsrl32
       // r6 - daddiu + dahi
       {0x00000000fffffffe, 3, 2},  // max_uint32 - 1
       // r2 - lui + ori + dsll
       // r6 - daddiu + dahi
       {0x00ffff000000fffe, 3, 3},
       // ori + dsll32 + ori
       {0x00000001fffffffe, 4, 2},  // max_uint32 << 1
       // r2 - lui + ori + dsll + ori
       // r6 - daddiu + dahi
-      {0x0000fffffffffffe, 5, 2},  // max_uint48 - 1
-      // r2 - ori + dsll + ori + dsll + ori
+      {0x0000fffffffffffe, 4, 2},  // max_uint48 - 1
+      // r2 - daddiu + dsll32 + ori + dsubu
+      // Loading imm directly would require ori + dsll + ori + dsll + ori.
+      // Optimized by loading -imm and using dsubu to get imm.
       // r6 - daddiu + dati
       {0xffffffff00000000, 2, 2},  // max_uint32 << 32
       // r2 - daddiu + dsll32
       // r6 - ori + dahi
       // We need ori to clear register before loading value using dahi.
       {0xffffffff80000000, 1, 1},  // min_int32
       // The test case above generates lui instruction.
       {0x0000000080000000, 2, 2},  // max_int32 + 1
       // r2 - ori + dsll
       // r6 - lui + dahi
       {0x0000800000000000, 2, 2},
       // ori + dsll32
       {0xffff800000000000, 2, 2},
       // r2 - daddiu + dsll32
       // r6 - ori + dahi
       {0xffff80000000ffff, 3, 2},
       // r2 - daddiu + dsll32 + ori
       // r6 - ori + dahi
       {0xffffff123000ffff, 3, 3},
       // daddiu + dsll + ori
       {0xffff00000000ffff, 3, 2},
       // r2 - daddiu + dsll32 + ori
       // r6 - ori + dati
       {0xffff8000ffff0000, 3, 2},
       // r2 - lui + ori + dsll
       // r6 - lui + dahi
+      {0x0000ffffffff0000, 4, 2},
+      // r2 - ori + dsll + ori + dsll
+      // r6 - lui + dati
       {0x1234ffff80000000, 3, 2},
       // r2 - lui + ori + dsll
       // r6 - lui + dati
       {0x1234ffff80010000, 5, 2},
       // r2 - lui + ori + dsll + ori + dsll
       // r6 - lui + dati
       {0xffff8000ffff8000, 2, 2},
       // r2 - daddiu + dinsu
       // r6 - daddiu + dahi
-      {0xffff0000ffff8000, 5, 3},
-      // r2 - lui + dsll + ori + dsll + ori
+      {0xffff0000ffff8000, 4, 3},
+      // r2 - ori + dsll32 + ori + dsubu
+      // Loading imm directly would require lui + dsll + ori + dsll + ori.
+      // Optimized by loading -imm and using dsubu to get imm.
       // r6 - daddiu + dahi + dati
       {0x8000000080000000, 2, 2},
       // lui + dinsu
       {0xabcd0000abcd0000, 2, 2},
       // lui + dinsu
       {0x8000800080008000, 3, 3},
       // lui + ori + dinsu
       {0xabcd1234abcd1234, 3, 3},
       // The test case above generates lui + ori + dinsu instruction sequence.
       {0xffff800080008000, 4, 3},
       // r2 - lui + ori + dsll + ori
       // r6 - lui + ori + dahi
       {0xffffabcd, 3, 2},
       // r2 - ori + dsll + ori
       // r6 - daddiu + dahi
       {0x1ffffabcd, 4, 2},
       // r2 - lui + ori + dsll + ori
       // r6 - daddiu + dahi
-      {0xffffffffabcd, 5, 2},
-      // r2 - ori + dsll + ori + dsll + ori
+      {0xffffffffabcd, 4, 2},
+      // r2 - daddiu + dsll32 + ori + dsubu
+      // Loading imm directly would require ori + dsll + ori + dsll + ori.
+      // Optimized by loading -imm and using dsubu to get imm.
       // r6 - daddiu + dati
-      {0x1ffffffffabcd, 6, 2},
-      // r2 - lui + ori + dsll + ori + dsll + ori
+      {0x1ffffffffabcd, 4, 2},
+      // r2 - daddiu + dsll32 + ori + dsubu
+      // Loading imm directly would require lui + ori + dsll + ori + dsll + ori.
+      // Optimized by loading -imm and using dsubu to get imm.
       // r6 - daddiu + dati
       {0xffff7fff80010000, 5, 2},
       // r2 - lui + ori + dsll + ori + dsll
       // r6 - lui + dahi
       // Here lui sets high 32 bits to 1 so dahi can be used to get target
       // value.
       {0x00007fff7fff0000, 3, 2},
       // r2 - lui + ori + dsll
       // r6 - lui + dahi
       // High 32 bits are not set so dahi can be used to get target value.
       {0xffff7fff7fff0000, 5, 3},
       // r2 - lui + ori + dsll + ori + dsll
       // r6 - lui + dahi + dati
       // High 32 bits are not set so just dahi can't be used to get target
       // value.
       {0x00007fff80010000, 3, 3},
       // r2 - lui + ori + dsll
       // r6 - lui + ori + dsll
       // High 32 bits are set so can't just use lui + dahi to get target value.
       {0x1234abcd87654321, 6, 4},
       // The test case above generates:
       // r2 - lui + ori + dsll + ori + dsll + ori instruction sequence,
       // r6 - lui + ori + dahi + dati.
       // Load using full instruction sequence.
+      {0xffff0000ffffffff, 3, 3},
+      // r2 - ori + dsll32 + nor
+      // Loading imm directly would require lui + dsll + ori + dsll + ori.
+      // Optimized by loading ~imm and using nor to get imm. Loading -imm would
+      // require one instruction more.
+      // r6 - daddiu + dahi + dati
   };
 
   size_t nr_test_cases = sizeof(tc) / sizeof(TestCase_li);
   for (size_t i = 0; i < nr_test_cases; ++i) {
     if (kArchVariant == kMips64r2) {
       CHECK_EQ(tc[i].imm,
                run_li_macro(tc[i].imm, OPTIMIZE_SIZE, tc[i].r2_num_instr));
     } else {
       CHECK_EQ(tc[i].imm,
                run_li_macro(tc[i].imm, OPTIMIZE_SIZE, tc[i].r6_num_instr));
@@ skipping 970 matching lines @@
   __ bind(&code_start);
   __ Subu(v0, zero_reg, Operand(imm));
   CHECK_EQ(assm.InstructionsGeneratedSince(&code_start), num_instr);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(isolate, &desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
+#ifdef OBJECT_PRINT
+  code->Print(std::cout);
+#endif
   F2 f = FUNCTION_CAST<F2>(code->entry());
 
   uint64_t res = reinterpret_cast<uint64_t>(
       CALL_GENERATED_CODE(isolate, f, 0, 0, 0, 0, 0));
 
   return res;
 }
 
 TEST(Subu) {
   CcTest::InitializeVM();
@@ skipping 59 matching lines @@
   __ bind(&code_start);
   __ Dsubu(v0, zero_reg, Operand(imm));
   CHECK_EQ(assm.InstructionsGeneratedSince(&code_start), num_instr);
   __ jr(ra);
   __ nop();
 
   CodeDesc desc;
   assm.GetCode(isolate, &desc);
   Handle<Code> code = isolate->factory()->NewCode(
       desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
+#ifdef OBJECT_PRINT
+  code->Print(std::cout);
+#endif
   F2 f = FUNCTION_CAST<F2>(code->entry());
 
   uint64_t res = reinterpret_cast<uint64_t>(
       CALL_GENERATED_CODE(isolate, f, 0, 0, 0, 0, 0));
 
   return res;
 }
 
 TEST(Dsubu) {
   CcTest::InitializeVM();
@@ skipping 43 matching lines @@
       // bit register, Dsubu gives a different result here.
       {0x7fffffffffffffff, 0x8000000000000001, 3},  // max_int64
       // r2 - Generates daddiu + dsrl + dsubu
       // r6 - Generates daddiu + dati + dsubu
       {0x8000000000000000, 0x8000000000000000, 3},  // min_int64
       // The test case above generates:
       // r2 - daddiu + dsrl32 + dsubu instruction sequence,
       // r6 - ori + dati + dsubu.
       // The result of 0 - min_int64 eqauls max_int64 + 1, which wraps around to
       // min_int64 again.
+      {0xffff0000ffffffff, 0x0000ffff00000001, 4},
+      // The test case above generates:
+      // r2 - ori + dsrl32 + ori + daddu instruction sequence,
+      // r6 - daddiu + dahi + dati + dsubu.
+      // For r2 loading imm would take more instructions than loading -imm so we
+      // can load -imm and add with daddu.
   };
 
   size_t nr_test_cases = sizeof(tc) / sizeof(TestCaseDsubu);
   for (size_t i = 0; i < nr_test_cases; ++i) {
     CHECK_EQ(tc[i].expected_res, run_Dsubu(tc[i].imm, tc[i].num_instr));
   }
 }
 
 uint64_t run_Dins(uint64_t imm, uint64_t source, uint16_t pos, uint16_t size) {
   Isolate* isolate = CcTest::i_isolate();
@@ skipping 601 matching lines @@
   };
 
   for (size_t i = 0; i < sizeof(tc) / sizeof(TestCaseMsaI8); ++i) {
     run_msa_i8(SHF_B, tc[i].input_lo, tc[i].input_hi, tc[i].i8);
     run_msa_i8(SHF_H, tc[i].input_lo, tc[i].input_hi, tc[i].i8);
     run_msa_i8(SHF_W, tc[i].input_lo, tc[i].input_hi, tc[i].i8);
   }
 }
 
 #undef __