Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(127)

Side by Side Diff: src/mips/simulator-mips.cc

Issue 2908753002: MIPS[64]: Implement insert.df and I8 instructions in simulator (Closed)
Patch Set: Review comments, rebase Created 3 years, 6 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/mips/simulator-mips.h ('k') | src/mips64/constants-mips64.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS 10 #if V8_TARGET_ARCH_MIPS
(...skipping 1792 matching lines...) Expand 10 before | Expand all | Expand 10 after
1803 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64 1803 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64
1804 ") dbl[0..1]:%e %e", 1804 ") dbl[0..1]:%e %e",
1805 v.d[0], v.d[1], icount_, v.df[0], v.df[1]); 1805 v.d[0], v.d[1], icount_, v.df[0], v.df[1]);
1806 break; 1806 break;
1807 default: 1807 default:
1808 UNREACHABLE(); 1808 UNREACHABLE();
1809 } 1809 }
1810 } 1810 }
1811 } 1811 }
1812 1812
1813 template <typename T>
1814 void Simulator::TraceMSARegWr(T* value) {
1815 if (::v8::internal::FLAG_trace_sim) {
1816 union {
1817 uint8_t b[kMSALanesByte];
1818 uint16_t h[kMSALanesHalf];
1819 uint32_t w[kMSALanesWord];
1820 uint64_t d[kMSALanesDword];
1821 float f[kMSALanesWord];
1822 double df[kMSALanesDword];
1823 } v;
1824 memcpy(v.b, value, kMSALanesByte);
1825
1826 if (std::is_same<T, int32_t>::value) {
1827 SNPrintF(trace_buf_,
1828 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64
1829 ") int32[0..3]:%" PRId32 " %" PRId32 " %" PRId32
1830 " %" PRId32,
1831 v.d[0], v.d[1], icount_, v.w[0], v.w[1], v.w[2], v.w[3]);
1832 } else if (std::is_same<T, float>::value) {
1833 SNPrintF(trace_buf_,
1834 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64
1835 ") flt[0..3]:%e %e %e %e",
1836 v.d[0], v.d[1], icount_, v.f[0], v.f[1], v.f[2], v.f[3]);
1837 } else if (std::is_same<T, double>::value) {
1838 SNPrintF(trace_buf_,
1839 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64
1840 ") dbl[0..1]:%e %e",
1841 v.d[0], v.d[1], icount_, v.df[0], v.df[1]);
1842 } else {
1843 SNPrintF(trace_buf_,
1844 "LO: %016" PRIx64 " HI: %016" PRIx64 " (%" PRIu64 ")",
1845 v.d[0], v.d[1], icount_);
1846 }
1847 }
1848 }
1849
1813 // TODO(plind): consider making icount_ printing a flag option. 1850 // TODO(plind): consider making icount_ printing a flag option.
1814 void Simulator::TraceMemRd(int32_t addr, int32_t value, TraceType t) { 1851 void Simulator::TraceMemRd(int32_t addr, int32_t value, TraceType t) {
1815 if (::v8::internal::FLAG_trace_sim) { 1852 if (::v8::internal::FLAG_trace_sim) {
1816 union { 1853 union {
1817 int32_t fmt_int32; 1854 int32_t fmt_int32;
1818 float fmt_float; 1855 float fmt_float;
1819 } v; 1856 } v;
1820 v.fmt_int32 = value; 1857 v.fmt_int32 = value;
1821 1858
1822 switch (t) { 1859 switch (t) {
(...skipping 2433 matching lines...) Expand 10 before | Expand all | Expand 10 after
4256 break; 4293 break;
4257 } 4294 }
4258 } 4295 }
4259 return df; 4296 return df;
4260 } 4297 }
4261 4298
4262 void Simulator::DecodeTypeMsaI8() { 4299 void Simulator::DecodeTypeMsaI8() {
4263 DCHECK(IsMipsArchVariant(kMips32r6)); 4300 DCHECK(IsMipsArchVariant(kMips32r6));
4264 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4301 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4265 uint32_t opcode = instr_.InstructionBits() & kMsaI8Mask; 4302 uint32_t opcode = instr_.InstructionBits() & kMsaI8Mask;
4303 int8_t i8 = instr_.MsaImm8Value();
4304 msa_reg_t ws, wd;
4266 4305
4267 switch (opcode) { 4306 switch (opcode) {
4268 case ANDI_B: 4307 case ANDI_B:
4308 get_msa_register(instr_.WsValue(), ws.b);
4309 for (int i = 0; i < kMSALanesByte; i++) {
4310 wd.b[i] = ws.b[i] & i8;
4311 }
4312 set_msa_register(instr_.WdValue(), wd.b);
4313 TraceMSARegWr(wd.b);
4314 break;
4269 case ORI_B: 4315 case ORI_B:
4316 get_msa_register(instr_.WsValue(), ws.b);
4317 for (int i = 0; i < kMSALanesByte; i++) {
4318 wd.b[i] = ws.b[i] | i8;
4319 }
4320 set_msa_register(instr_.WdValue(), wd.b);
4321 TraceMSARegWr(wd.b);
4322 break;
4270 case NORI_B: 4323 case NORI_B:
4324 get_msa_register(instr_.WsValue(), ws.b);
4325 for (int i = 0; i < kMSALanesByte; i++) {
4326 wd.b[i] = ~(ws.b[i] | i8);
4327 }
4328 set_msa_register(instr_.WdValue(), wd.b);
4329 TraceMSARegWr(wd.b);
4330 break;
4271 case XORI_B: 4331 case XORI_B:
4332 get_msa_register(instr_.WsValue(), ws.b);
4333 for (int i = 0; i < kMSALanesByte; i++) {
4334 wd.b[i] = ws.b[i] ^ i8;
4335 }
4336 set_msa_register(instr_.WdValue(), wd.b);
4337 TraceMSARegWr(wd.b);
4338 break;
4272 case BMNZI_B: 4339 case BMNZI_B:
4340 get_msa_register(instr_.WsValue(), ws.b);
4341 get_msa_register(instr_.WdValue(), wd.b);
4342 for (int i = 0; i < kMSALanesByte; i++) {
4343 wd.b[i] = (ws.b[i] & i8) | (wd.b[i] & ~i8);
4344 }
4345 set_msa_register(instr_.WdValue(), wd.b);
4346 TraceMSARegWr(wd.b);
4347 break;
4273 case BMZI_B: 4348 case BMZI_B:
4349 get_msa_register(instr_.WsValue(), ws.b);
4350 get_msa_register(instr_.WdValue(), wd.b);
4351 for (int i = 0; i < kMSALanesByte; i++) {
4352 wd.b[i] = (ws.b[i] & ~i8) | (wd.b[i] & i8);
4353 }
4354 set_msa_register(instr_.WdValue(), wd.b);
4355 TraceMSARegWr(wd.b);
4356 break;
4274 case BSELI_B: 4357 case BSELI_B:
4358 get_msa_register(instr_.WsValue(), ws.b);
4359 get_msa_register(instr_.WdValue(), wd.b);
4360 for (int i = 0; i < kMSALanesByte; i++) {
4361 wd.b[i] = (ws.b[i] & ~wd.b[i]) | (wd.b[i] & i8);
4362 }
4363 set_msa_register(instr_.WdValue(), wd.b);
4364 TraceMSARegWr(wd.b);
4365 break;
4275 case SHF_B: 4366 case SHF_B:
4367 get_msa_register(instr_.WsValue(), ws.b);
4368 for (int i = 0; i < kMSALanesByte; i++) {
4369 int j = i % 4;
4370 int k = (i8 >> (2 * j)) & 0x3;
4371 wd.b[i] = ws.b[i - j + k];
4372 }
4373 set_msa_register(instr_.WdValue(), wd.b);
4374 TraceMSARegWr(wd.b);
4375 break;
4276 case SHF_H: 4376 case SHF_H:
4377 get_msa_register(instr_.WsValue(), ws.h);
4378 for (int i = 0; i < kMSALanesHalf; i++) {
4379 int j = i % 4;
4380 int k = (i8 >> (2 * j)) & 0x3;
4381 wd.h[i] = ws.h[i - j + k];
4382 }
4383 set_msa_register(instr_.WdValue(), wd.h);
4384 TraceMSARegWr(wd.h);
4385 break;
4277 case SHF_W: 4386 case SHF_W:
4278 UNIMPLEMENTED(); 4387 get_msa_register(instr_.WsValue(), ws.w);
4388 for (int i = 0; i < kMSALanesWord; i++) {
4389 int j = (i8 >> (2 * i)) & 0x3;
4390 wd.w[i] = ws.w[j];
4391 }
4392 set_msa_register(instr_.WdValue(), wd.w);
4393 TraceMSARegWr(wd.w);
4279 break; 4394 break;
4280 default: 4395 default:
4281 UNREACHABLE(); 4396 UNREACHABLE();
4282 } 4397 }
4283 } 4398 }
4284 4399
4285 void Simulator::DecodeTypeMsaI5() { 4400 void Simulator::DecodeTypeMsaI5() {
4286 DCHECK(IsMipsArchVariant(kMips32r6)); 4401 DCHECK(IsMipsArchVariant(kMips32r6));
4287 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4402 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4288 uint32_t opcode = instr_.InstructionBits() & kMsaI5Mask; 4403 uint32_t opcode = instr_.InstructionBits() & kMsaI5Mask;
(...skipping 29 matching lines...) Expand all
4318 } 4433 }
4319 4434
4320 void Simulator::DecodeTypeMsaELM() { 4435 void Simulator::DecodeTypeMsaELM() {
4321 DCHECK(IsMipsArchVariant(kMips32r6)); 4436 DCHECK(IsMipsArchVariant(kMips32r6));
4322 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4437 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4323 uint32_t opcode = instr_.InstructionBits() & kMsaELMMask; 4438 uint32_t opcode = instr_.InstructionBits() & kMsaELMMask;
4324 int32_t n = instr_.MsaElmNValue(); 4439 int32_t n = instr_.MsaElmNValue();
4325 int32_t alu_out; 4440 int32_t alu_out;
4326 switch (opcode) { 4441 switch (opcode) {
4327 case COPY_S: 4442 case COPY_S:
4328 case COPY_U: 4443 case COPY_U: {
4444 msa_reg_t ws;
4329 switch (DecodeMsaDataFormat()) { 4445 switch (DecodeMsaDataFormat()) {
4330 case MSA_BYTE: { 4446 case MSA_BYTE: {
4331 DCHECK(n < 16); 4447 DCHECK(n < kMSALanesByte);
4332 int8_t ws[16]; 4448 get_msa_register(instr_.WsValue(), ws.b);
4333 get_msa_register(instr_.WsValue(), ws); 4449 alu_out = static_cast<int32_t>(ws.b[n]);
4334 alu_out = static_cast<int32_t>(ws[n]);
4335 SetResult(wd_reg(), (opcode == COPY_U) ? alu_out & 0xFFu : alu_out); 4450 SetResult(wd_reg(), (opcode == COPY_U) ? alu_out & 0xFFu : alu_out);
4336 break; 4451 break;
4337 } 4452 }
4338 case MSA_HALF: { 4453 case MSA_HALF: {
4339 DCHECK(n < 8); 4454 DCHECK(n < kMSALanesHalf);
4340 int16_t ws[8]; 4455 get_msa_register(instr_.WsValue(), ws.h);
4341 get_msa_register(instr_.WsValue(), ws); 4456 alu_out = static_cast<int32_t>(ws.h[n]);
4342 alu_out = static_cast<int32_t>(ws[n]);
4343 SetResult(wd_reg(), (opcode == COPY_U) ? alu_out & 0xFFFFu : alu_out); 4457 SetResult(wd_reg(), (opcode == COPY_U) ? alu_out & 0xFFFFu : alu_out);
4344 break; 4458 break;
4345 } 4459 }
4346 case MSA_WORD: { 4460 case MSA_WORD: {
4347 DCHECK(n < 4); 4461 DCHECK(n < kMSALanesWord);
4348 int32_t ws[4]; 4462 get_msa_register(instr_.WsValue(), ws.w);
4349 get_msa_register(instr_.WsValue(), ws); 4463 alu_out = static_cast<int32_t>(ws.w[n]);
4350 alu_out = static_cast<int32_t>(ws[n]);
4351 SetResult(wd_reg(), alu_out); 4464 SetResult(wd_reg(), alu_out);
4352 break; 4465 break;
4353 } 4466 }
4354 default: 4467 default:
4355 UNREACHABLE(); 4468 UNREACHABLE();
4356 } 4469 }
4357 break; 4470 } break;
4471 case INSERT: {
4472 msa_reg_t wd;
4473 switch (DecodeMsaDataFormat()) {
4474 case MSA_BYTE: {
4475 DCHECK(n < kMSALanesByte);
4476 int32_t rs = get_register(instr_.WsValue());
4477 get_msa_register(instr_.WdValue(), wd.b);
4478 wd.b[n] = rs & 0xFFu;
4479 set_msa_register(instr_.WdValue(), wd.b);
4480 TraceMSARegWr(wd.b);
4481 break;
4482 }
4483 case MSA_HALF: {
4484 DCHECK(n < kMSALanesHalf);
4485 int32_t rs = get_register(instr_.WsValue());
4486 get_msa_register(instr_.WdValue(), wd.h);
4487 wd.h[n] = rs & 0xFFFFu;
4488 set_msa_register(instr_.WdValue(), wd.h);
4489 TraceMSARegWr(wd.h);
4490 break;
4491 }
4492 case MSA_WORD: {
4493 DCHECK(n < kMSALanesWord);
4494 int32_t rs = get_register(instr_.WsValue());
4495 get_msa_register(instr_.WdValue(), wd.w);
4496 wd.w[n] = rs;
4497 set_msa_register(instr_.WdValue(), wd.w);
4498 TraceMSARegWr(wd.w);
4499 break;
4500 }
4501 default:
4502 UNREACHABLE();
4503 }
4504 } break;
4358 case SLDI: 4505 case SLDI:
4359 case SPLATI: 4506 case SPLATI:
4360 case INSERT:
4361 case INSVE: 4507 case INSVE:
4362 UNIMPLEMENTED(); 4508 UNIMPLEMENTED();
4363 break; 4509 break;
4364 default: 4510 default:
4365 UNREACHABLE(); 4511 UNREACHABLE();
4366 } 4512 }
4367 } 4513 }
4368 4514
4369 void Simulator::DecodeTypeMsaBIT() { 4515 void Simulator::DecodeTypeMsaBIT() {
4370 DCHECK(IsMipsArchVariant(kMips32r6)); 4516 DCHECK(IsMipsArchVariant(kMips32r6));
(...skipping 177 matching lines...) Expand 10 before | Expand all | Expand 10 after
4548 break; 4694 break;
4549 default: 4695 default:
4550 UNREACHABLE(); 4696 UNREACHABLE();
4551 } 4697 }
4552 } 4698 }
4553 4699
4554 void Simulator::DecodeTypeMsa2R() { 4700 void Simulator::DecodeTypeMsa2R() {
4555 DCHECK(IsMipsArchVariant(kMips32r6)); 4701 DCHECK(IsMipsArchVariant(kMips32r6));
4556 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4702 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4557 uint32_t opcode = instr_.InstructionBits() & kMsa2RMask; 4703 uint32_t opcode = instr_.InstructionBits() & kMsa2RMask;
4704 msa_reg_t wd;
4558 switch (opcode) { 4705 switch (opcode) {
4559 case FILL: 4706 case FILL:
4560 switch (DecodeMsaDataFormat()) { 4707 switch (DecodeMsaDataFormat()) {
4561 case MSA_BYTE: { 4708 case MSA_BYTE: {
4562 int8_t wd[16];
4563 int32_t rs = get_register(instr_.WsValue()); 4709 int32_t rs = get_register(instr_.WsValue());
4564 for (int i = 0; i < 16; i++) { 4710 for (int i = 0; i < kMSALanesByte; i++) {
4565 wd[i] = rs & 0xFFu; 4711 wd.b[i] = rs & 0xFFu;
4566 } 4712 }
4567 set_msa_register(instr_.WdValue(), wd); 4713 set_msa_register(instr_.WdValue(), wd.b);
4568 TraceMSARegWr(wd, BYTE); 4714 TraceMSARegWr(wd.b);
4569 break; 4715 break;
4570 } 4716 }
4571 case MSA_HALF: { 4717 case MSA_HALF: {
4572 int16_t wd[8];
4573 int32_t rs = get_register(instr_.WsValue()); 4718 int32_t rs = get_register(instr_.WsValue());
4574 for (int i = 0; i < 8; i++) { 4719 for (int i = 0; i < kMSALanesHalf; i++) {
4575 wd[i] = rs & 0xFFFFu; 4720 wd.h[i] = rs & 0xFFFFu;
4576 } 4721 }
4577 set_msa_register(instr_.WdValue(), wd); 4722 set_msa_register(instr_.WdValue(), wd.h);
4578 TraceMSARegWr(wd, HALF); 4723 TraceMSARegWr(wd.h);
4579 break; 4724 break;
4580 } 4725 }
4581 case MSA_WORD: { 4726 case MSA_WORD: {
4582 int32_t wd[4];
4583 int32_t rs = get_register(instr_.WsValue()); 4727 int32_t rs = get_register(instr_.WsValue());
4584 for (int i = 0; i < 4; i++) { 4728 for (int i = 0; i < kMSALanesWord; i++) {
4585 wd[i] = rs; 4729 wd.w[i] = rs;
4586 } 4730 }
4587 set_msa_register(instr_.WdValue(), wd); 4731 set_msa_register(instr_.WdValue(), wd.w);
4588 TraceMSARegWr(wd, WORD); 4732 TraceMSARegWr(wd.w);
4589 break; 4733 break;
4590 } 4734 }
4591 default: 4735 default:
4592 UNREACHABLE(); 4736 UNREACHABLE();
4593 } 4737 }
4594 break; 4738 break;
4595 case PCNT: 4739 case PCNT:
4596 case NLOC: 4740 case NLOC:
4597 case NLZC: 4741 case NLZC:
4598 UNIMPLEMENTED(); 4742 UNIMPLEMENTED();
(...skipping 822 matching lines...) Expand 10 before | Expand all | Expand 10 after
5421 5565
5422 5566
5423 #undef UNSUPPORTED 5567 #undef UNSUPPORTED
5424 5568
5425 } // namespace internal 5569 } // namespace internal
5426 } // namespace v8 5570 } // namespace v8
5427 5571
5428 #endif // USE_SIMULATOR 5572 #endif // USE_SIMULATOR
5429 5573
5430 #endif // V8_TARGET_ARCH_MIPS 5574 #endif // V8_TARGET_ARCH_MIPS
OLDNEW
« no previous file with comments | « src/mips/simulator-mips.h ('k') | src/mips64/constants-mips64.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698