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Side by Side Diff: src/mips64/simulator-mips64.cc

Issue 2908753002: MIPS[64]: Implement insert.df and I8 instructions in simulator (Closed)
Patch Set: Created 3 years, 6 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
(...skipping 4467 matching lines...) Expand 10 before | Expand all | Expand 10 after
4478 break; 4478 break;
4479 } 4479 }
4480 } 4480 }
4481 return df; 4481 return df;
4482 } 4482 }
4483 4483
4484 void Simulator::DecodeTypeMsaI8() { 4484 void Simulator::DecodeTypeMsaI8() {
4485 DCHECK(kArchVariant == kMips64r6); 4485 DCHECK(kArchVariant == kMips64r6);
4486 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4486 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4487 uint32_t opcode = instr_.InstructionBits() & kMsaI8Mask; 4487 uint32_t opcode = instr_.InstructionBits() & kMsaI8Mask;
4488 int8_t i8 = instr_.MsaImm8Value() & 0xFFu;
4488 4489
4489 switch (opcode) { 4490 switch (opcode) {
4490 case ANDI_B: 4491 case ANDI_B: {
4491 case ORI_B: 4492 int8_t ws[16], wd[16];
4492 case NORI_B: 4493 get_msa_register(instr_.WsValue(), ws);
4493 case XORI_B: 4494 for (int i = 0; i < 16; i++) {
4494 case BMNZI_B: 4495 wd[i] = ws[i] & i8;
4495 case BMZI_B: 4496 }
4496 case BSELI_B: 4497 set_msa_register(instr_.WdValue(), wd);
4497 case SHF_B: 4498 TraceMSARegWr(wd, BYTE);
4498 case SHF_H: 4499 } break;
4499 case SHF_W: 4500 case ORI_B: {
4500 UNIMPLEMENTED(); 4501 int8_t ws[16], wd[16];
4501 break; 4502 get_msa_register(instr_.WsValue(), ws);
4503 for (int i = 0; i < 16; i++) {
4504 wd[i] = ws[i] | i8;
4505 }
4506 set_msa_register(instr_.WdValue(), wd);
4507 TraceMSARegWr(wd, BYTE);
4508 } break;
4509 case NORI_B: {
4510 int8_t ws[16], wd[16];
4511 get_msa_register(instr_.WsValue(), ws);
4512 for (int i = 0; i < 16; i++) {
4513 wd[i] = ~(ws[i] | i8);
4514 }
4515 set_msa_register(instr_.WdValue(), wd);
4516 TraceMSARegWr(wd, BYTE);
4517 } break;
4518 case XORI_B: {
4519 int8_t ws[16], wd[16];
4520 get_msa_register(instr_.WsValue(), ws);
4521 for (int i = 0; i < 16; i++) {
4522 wd[i] = ws[i] ^ i8;
4523 }
4524 set_msa_register(instr_.WdValue(), wd);
4525 TraceMSARegWr(wd, BYTE);
4526 } break;
4527 case BMNZI_B: {
4528 int8_t ws[16], wd[16];
4529 get_msa_register(instr_.WsValue(), ws);
4530 get_msa_register(instr_.WdValue(), wd);
4531 for (int i = 0; i < 16; i++) {
4532 wd[i] = (ws[i] & i8) | (wd[i] & ~i8);
4533 }
4534 set_msa_register(instr_.WdValue(), wd);
4535 TraceMSARegWr(wd, BYTE);
4536 } break;
4537 case BMZI_B: {
4538 int8_t ws[16], wd[16];
4539 get_msa_register(instr_.WsValue(), ws);
4540 get_msa_register(instr_.WdValue(), wd);
4541 for (int i = 0; i < 16; i++) {
4542 wd[i] = (ws[i] & ~i8) | (wd[i] & i8);
4543 }
4544 set_msa_register(instr_.WdValue(), wd);
4545 TraceMSARegWr(wd, BYTE);
4546 } break;
4547 case BSELI_B: {
4548 int8_t ws[16], wd[16];
4549 get_msa_register(instr_.WsValue(), ws);
4550 get_msa_register(instr_.WdValue(), wd);
4551 for (int i = 0; i < 16; i++) {
4552 wd[i] = (ws[i] & ~wd[i]) | (wd[i] & i8);
4553 }
4554 set_msa_register(instr_.WdValue(), wd);
4555 TraceMSARegWr(wd, BYTE);
4556 } break;
4557 case SHF_B: {
4558 int8_t ws[16], wd[16];
4559 get_msa_register(instr_.WsValue(), ws);
4560 for (int i = 0; i < 16; i++) {
4561 int j = i % 4;
4562 int k = (i8 >> (2 * j)) & 0x3;
4563 wd[i] = ws[i - j + k];
4564 }
4565 set_msa_register(instr_.WdValue(), wd);
4566 TraceMSARegWr(wd, BYTE);
4567 } break;
4568 case SHF_H: {
4569 int16_t ws[8], wd[8];
4570 get_msa_register(instr_.WsValue(), ws);
4571 for (int i = 0; i < 8; i++) {
4572 int j = i % 4;
4573 int k = (i8 >> (2 * j)) & 0x3;
4574 wd[i] = ws[i - j + k];
4575 }
4576 set_msa_register(instr_.WdValue(), wd);
4577 TraceMSARegWr(wd, HALF);
4578 } break;
4579 case SHF_W: {
4580 int32_t ws[4], wd[4];
4581 get_msa_register(instr_.WsValue(), ws);
4582 for (int i = 0; i < 4; i++) {
4583 int j = (i8 >> (2 * i)) & 0x3;
4584 wd[i] = ws[j];
4585 }
4586 set_msa_register(instr_.WdValue(), wd);
4587 TraceMSARegWr(wd, WORD);
4588 } break;
4502 default: 4589 default:
4503 UNREACHABLE(); 4590 UNREACHABLE();
4504 } 4591 }
4505 } 4592 }
4506 4593
4507 void Simulator::DecodeTypeMsaI5() { 4594 void Simulator::DecodeTypeMsaI5() {
4508 DCHECK(kArchVariant == kMips64r6); 4595 DCHECK(kArchVariant == kMips64r6);
4509 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD)); 4596 DCHECK(CpuFeatures::IsSupported(MIPS_SIMD));
4510 uint32_t opcode = instr_.InstructionBits() & kMsaI5Mask; 4597 uint32_t opcode = instr_.InstructionBits() & kMsaI5Mask;
4511 4598
(...skipping 67 matching lines...) Expand 10 before | Expand all | Expand 10 after
4579 int64_t ws[2]; 4666 int64_t ws[2];
4580 get_msa_register(instr_.WsValue(), ws); 4667 get_msa_register(instr_.WsValue(), ws);
4581 alu_out = static_cast<int64_t>(ws[n]); 4668 alu_out = static_cast<int64_t>(ws[n]);
4582 SetResult(wd_reg(), alu_out); 4669 SetResult(wd_reg(), alu_out);
4583 break; 4670 break;
4584 } 4671 }
4585 default: 4672 default:
4586 UNREACHABLE(); 4673 UNREACHABLE();
4587 } 4674 }
4588 break; 4675 break;
4676 case INSERT:
4677 switch (DecodeMsaDataFormat()) {
4678 case MSA_BYTE: {
4679 DCHECK(n < 16);
4680 int8_t wd[16];
4681 int64_t rs = get_register(instr_.WsValue());
4682 get_msa_register(instr_.WdValue(), wd);
4683 wd[n] = rs & 0xFFu;
4684 set_msa_register(instr_.WdValue(), wd);
4685 TraceMSARegWr(wd, BYTE);
4686 break;
4687 }
4688 case MSA_HALF: {
4689 DCHECK(n < 8);
4690 int16_t wd[8];
4691 int64_t rs = get_register(instr_.WsValue());
4692 get_msa_register(instr_.WdValue(), wd);
4693 wd[n] = rs & 0xFFFFu;
4694 set_msa_register(instr_.WdValue(), wd);
4695 TraceMSARegWr(wd, HALF);
4696 break;
4697 }
4698 case MSA_WORD: {
4699 DCHECK(n < 4);
4700 int32_t wd[4];
4701 int64_t rs = get_register(instr_.WsValue());
4702 get_msa_register(instr_.WdValue(), wd);
4703 wd[n] = rs & 0xFFFFFFFFu;
4704 set_msa_register(instr_.WdValue(), wd);
4705 TraceMSARegWr(wd, WORD);
4706 break;
4707 }
4708 case MSA_DWORD: {
4709 DCHECK(n < 2);
4710 int64_t wd[2];
4711 int64_t rs = get_register(instr_.WsValue());
4712 get_msa_register(instr_.WdValue(), wd);
4713 wd[n] = rs;
4714 set_msa_register(instr_.WdValue(), wd);
4715 TraceMSARegWr(wd, DWORD);
4716 break;
4717 }
4718 default:
4719 UNREACHABLE();
4720 }
4721 break;
4589 case SLDI: 4722 case SLDI:
4590 case SPLATI: 4723 case SPLATI:
4591 case INSERT:
4592 case INSVE: 4724 case INSVE:
4593 UNIMPLEMENTED(); 4725 UNIMPLEMENTED();
4594 break; 4726 break;
4595 default: 4727 default:
4596 UNREACHABLE(); 4728 UNREACHABLE();
4597 } 4729 }
4598 } 4730 }
4599 4731
4600 void Simulator::DecodeTypeMsaBIT() { 4732 void Simulator::DecodeTypeMsaBIT() {
4601 DCHECK(kArchVariant == kMips64r6); 4733 DCHECK(kArchVariant == kMips64r6);
(...skipping 1162 matching lines...) Expand 10 before | Expand all | Expand 10 after
5764 } 5896 }
5765 5897
5766 5898
5767 #undef UNSUPPORTED 5899 #undef UNSUPPORTED
5768 } // namespace internal 5900 } // namespace internal
5769 } // namespace v8 5901 } // namespace v8
5770 5902
5771 #endif // USE_SIMULATOR 5903 #endif // USE_SIMULATOR
5772 5904
5773 #endif // V8_TARGET_ARCH_MIPS64 5905 #endif // V8_TARGET_ARCH_MIPS64
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