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1 /* | 1 /* |
2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. | 2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. |
3 * | 3 * |
4 * Use of this source code is governed by a BSD-style license | 4 * Use of this source code is governed by a BSD-style license |
5 * that can be found in the LICENSE file in the root of the source | 5 * that can be found in the LICENSE file in the root of the source |
6 * tree. An additional intellectual property rights grant can be found | 6 * tree. An additional intellectual property rights grant can be found |
7 * in the file PATENTS. All contributing project authors may | 7 * in the file PATENTS. All contributing project authors may |
8 * be found in the AUTHORS file in the root of the source tree. | 8 * be found in the AUTHORS file in the root of the source tree. |
9 */ | 9 */ |
10 | 10 |
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610 clip_pixel(ROUND_POWER_OF_TWO(temp_out[j], 5) | 610 clip_pixel(ROUND_POWER_OF_TWO(temp_out[j], 5) |
611 + dest[j * dest_stride + i]); | 611 + dest[j * dest_stride + i]); |
612 } | 612 } |
613 break; | 613 break; |
614 default: | 614 default: |
615 printf("vp9_short_iht8x8_add_dspr2 : Invalid tx_type\n"); | 615 printf("vp9_short_iht8x8_add_dspr2 : Invalid tx_type\n"); |
616 break; | 616 break; |
617 } | 617 } |
618 } | 618 } |
619 | 619 |
620 void vp9_idct8x8_10_add_dspr2(const int16_t *input, uint8_t *dest, | 620 void vp9_idct8x8_12_add_dspr2(const int16_t *input, uint8_t *dest, |
621 int dest_stride) { | 621 int dest_stride) { |
622 DECLARE_ALIGNED(32, int16_t, out[8 * 8]); | 622 DECLARE_ALIGNED(32, int16_t, out[8 * 8]); |
623 int16_t *outptr = out; | 623 int16_t *outptr = out; |
624 uint32_t pos = 45; | 624 uint32_t pos = 45; |
625 | 625 |
626 /* bit positon for extract from acc */ | 626 /* bit positon for extract from acc */ |
627 __asm__ __volatile__ ( | 627 __asm__ __volatile__ ( |
628 "wrdsp %[pos], 1 \n\t" | 628 "wrdsp %[pos], 1 \n\t" |
629 : | 629 : |
630 : [pos] "r" (pos) | 630 : [pos] "r" (pos) |
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736 | 736 |
737 : [t1] "=&r" (t1), [t2] "=&r" (t2), | 737 : [t1] "=&r" (t1), [t2] "=&r" (t2), |
738 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2), | 738 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2), |
739 [dest] "+r" (dest) | 739 [dest] "+r" (dest) |
740 : [dest_stride] "r" (dest_stride), [vector_a1] "r" (vector_a1) | 740 : [dest_stride] "r" (dest_stride), [vector_a1] "r" (vector_a1) |
741 ); | 741 ); |
742 } | 742 } |
743 } | 743 } |
744 } | 744 } |
745 #endif // #if HAVE_DSPR2 | 745 #endif // #if HAVE_DSPR2 |
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