[compiler] Delay allocation of code-embedded heap numbers.

src/arm64/assembler-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
 #define V8_ARM64_ASSEMBLER_ARM64_H_
 
 #include <deque>
 #include <list>
 #include <map>
@@ skipping 532 matching lines @@
                  Shift shift = LSL,
                  unsigned shift_amount = 0);  // NOLINT(runtime/explicit)
 
   // rm, <extend> {#<shift_amount>}
   // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
   //       <shift_amount> is uint2_t.
   inline Operand(Register reg,
                  Extend extend,
                  unsigned shift_amount = 0);
 
+  static Operand EmbeddedNumber(double value);  // Smi or HeapNumber.
+
+  bool is_heap_number() const {
+    DCHECK_IMPLIES(is_heap_number_, reg_.Is(NoReg));
+    DCHECK_IMPLIES(is_heap_number_,
+                   immediate_.rmode() == RelocInfo::EMBEDDED_OBJECT);
+    return is_heap_number_;
+  }
+
+  double heap_number() const {
+    DCHECK(is_heap_number());
+    return bit_cast<double>(immediate_.value());
+  }
+
   template<typename T>
   inline explicit Operand(Handle<T> handle);
 
   // Implicit constructor for all int types, ExternalReference, and Smi.
   template<typename T>
   inline Operand(T t);  // NOLINT(runtime/explicit)
 
   // Implicit constructor for int types.
   template<typename T>
   inline Operand(T t, RelocInfo::Mode rmode);
@@ skipping 20 matching lines @@
   // Helpers
   inline static Operand UntagSmi(Register smi);
   inline static Operand UntagSmiAndScale(Register smi, int scale);
 
  private:
   Immediate immediate_;
   Register reg_;
   Shift shift_;
   Extend extend_;
   unsigned shift_amount_;
+  bool is_heap_number_ = false;
 };
 
 
 // MemOperand represents a memory operand in a load or store instruction.
 class MemOperand {
  public:
   inline MemOperand();
   inline explicit MemOperand(Register base,
                              int64_t offset = 0,
                              AddrMode addrmode = Offset);
@@ skipping 130 matching lines @@
   // In order to avoid any accidental transfer of state, Reset DCHECKs that the
   // constant pool is not blocked.
   void Reset();
 
   // GetCode emits any pending (non-emitted) code and fills the descriptor
   // desc. GetCode() is idempotent; it returns the same result if no other
   // Assembler functions are invoked in between GetCode() calls.
   //
   // The descriptor (desc) can be NULL. In that case, the code is finalized as
   // usual, but the descriptor is not populated.
-  void GetCode(CodeDesc* desc);
+  void GetCode(Isolate* isolate, CodeDesc* desc);
 
   // Insert the smallest number of nop instructions
   // possible to align the pc offset to a multiple
   // of m. m must be a power of 2 (>= 4).
   void Align(int m);
   // Insert the smallest number of zero bytes possible to align the pc offset
   // to a mulitple of m. m must be a power of 2 (>= 2).
   void DataAlign(int m);
 
   inline void Unreachable();
@@ skipping 163 matching lines @@
   // and cause the version of the code with debugger support to have pools
   // generated in different places.
   // Recording the position and size of emitted pools allows to correctly
   // compute the offset mappings between the different versions of a function in
   // all situations.
   //
   // The parameter indicates the size of the pool (in bytes), including
   // the marker and branch over the data.
   void RecordConstPool(int size);
 
+  // Patch the dummy heap number that we emitted during code assembly in the
+  // constant pool entry referenced by {pc}. Replace it with the actual heap
+  // object (handle).
+  static void set_heap_number(Handle<HeapObject> number, Address pc);
 
   // Instruction set functions ------------------------------------------------
 
   // Branch / Jump instructions.
   // For branches offsets are scaled, i.e. they in instrcutions not in bytes.
   // Branch to register.
   void br(const Register& xn);
 
   // Branch-link to register.
   void blr(const Register& xn);
@@ skipping 416 matching lines @@
            const MemOperand& dst);
 
   // Load word pair with sign extension.
   void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
 
   // Load literal to register from a pc relative address.
   void ldr_pcrel(const CPURegister& rt, int imm19);
 
   // Load literal to register.
   void ldr(const CPURegister& rt, const Immediate& imm);
+  void ldr(const CPURegister& rt, const Operand& operand);
 
   // Load-acquire word.
   void ldar(const Register& rt, const Register& rn);
 
   // Load-acquire exclusive word.
   void ldaxr(const Register& rt, const Register& rn);
 
   // Store-release word.
   void stlr(const Register& rt, const Register& rn);
 
@@ skipping 832 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBufferSpace();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_H_