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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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273 IsPatchedDebugBreakSlotSequence()) { | 273 IsPatchedDebugBreakSlotSequence()) { |
274 StaticVisitor::VisitDebugTarget(heap, this); | 274 StaticVisitor::VisitDebugTarget(heap, this); |
275 } else if (RelocInfo::IsRuntimeEntry(mode)) { | 275 } else if (RelocInfo::IsRuntimeEntry(mode)) { |
276 StaticVisitor::VisitRuntimeEntry(this); | 276 StaticVisitor::VisitRuntimeEntry(this); |
277 } | 277 } |
278 } | 278 } |
279 | 279 |
280 | 280 |
281 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { | 281 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { |
282 rm_ = no_reg; | 282 rm_ = no_reg; |
283 imm32_ = immediate; | 283 value_.immediate = immediate; |
284 rmode_ = rmode; | 284 rmode_ = rmode; |
285 } | 285 } |
286 | 286 |
287 Operand Operand::Zero() { return Operand(static_cast<int32_t>(0)); } | 287 Operand Operand::Zero() { return Operand(static_cast<int32_t>(0)); } |
288 | 288 |
289 Operand::Operand(const ExternalReference& f) { | 289 Operand::Operand(const ExternalReference& f) { |
290 rm_ = no_reg; | 290 rm_ = no_reg; |
291 imm32_ = reinterpret_cast<int32_t>(f.address()); | 291 value_.immediate = reinterpret_cast<int32_t>(f.address()); |
292 rmode_ = RelocInfo::EXTERNAL_REFERENCE; | 292 rmode_ = RelocInfo::EXTERNAL_REFERENCE; |
293 } | 293 } |
294 | 294 |
295 | 295 |
296 Operand::Operand(Smi* value) { | 296 Operand::Operand(Smi* value) { |
297 rm_ = no_reg; | 297 rm_ = no_reg; |
298 imm32_ = reinterpret_cast<intptr_t>(value); | 298 value_.immediate = reinterpret_cast<intptr_t>(value); |
299 rmode_ = RelocInfo::NONE32; | 299 rmode_ = RelocInfo::NONE32; |
300 } | 300 } |
301 | 301 |
302 | 302 |
303 Operand::Operand(Register rm) { | 303 Operand::Operand(Register rm) { |
304 rm_ = rm; | 304 rm_ = rm; |
305 rs_ = no_reg; | 305 rs_ = no_reg; |
306 shift_op_ = LSL; | 306 shift_op_ = LSL; |
307 shift_imm_ = 0; | 307 shift_imm_ = 0; |
308 } | 308 } |
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506 Address constant_pool = code ? code->constant_pool() : NULL; | 506 Address constant_pool = code ? code->constant_pool() : NULL; |
507 set_target_address_at(isolate, pc, constant_pool, target, icache_flush_mode); | 507 set_target_address_at(isolate, pc, constant_pool, target, icache_flush_mode); |
508 } | 508 } |
509 | 509 |
510 EnsureSpace::EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } | 510 EnsureSpace::EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } |
511 | 511 |
512 } // namespace internal | 512 } // namespace internal |
513 } // namespace v8 | 513 } // namespace v8 |
514 | 514 |
515 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ | 515 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ |
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