Add SSE4 optimization of S32A_Opaque_Blitrow

src/opts/opts_check_x86.cpp

 /*
  * Copyright 2009 The Android Open Source Project
  *
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "SkBitmapFilter_opts_SSE2.h"
 #include "SkBitmapProcState_opts_SSE2.h"
 #include "SkBitmapProcState_opts_SSSE3.h"
 #include "SkBlitMask.h"
 #include "SkBlitRect_opts_SSE2.h"
 #include "SkBlitRow.h"
 #include "SkBlitRow_opts_SSE2.h"
+#include "SkBlitRow_opts_SSE4.h"
 #include "SkBlurImage_opts_SSE2.h"
 #include "SkMorphology_opts.h"
 #include "SkMorphology_opts_SSE2.h"
 #include "SkRTConf.h"
 #include "SkUtils.h"
 #include "SkUtils_opts_SSE2.h"
 #include "SkXfermode.h"
 #include "SkXfermode_proccoeff.h"
 
 #if defined(_MSC_VER) && defined(_WIN64)
@@ skipping 50 matching lines @@
 
 /* Fetch the SIMD level directly from the CPU, at run-time.
  * Only checks the levels needed by the optimizations in this file.
  */
 static int get_SIMD_level() {
     int cpu_info[4] = { 0 };
 
     getcpuid(1, cpu_info);
     if ((cpu_info[2] & (1<<20)) != 0) {
         return SK_CPU_SSE_LEVEL_SSE42;
+    } else if ((cpu_info[2] & (1<<19)) != 0) {
+        return SK_CPU_SSE_LEVEL_SSE41;
     } else if ((cpu_info[2] & (1<<9)) != 0) {
         return SK_CPU_SSE_LEVEL_SSSE3;
     } else if ((cpu_info[3] & (1<<26)) != 0) {
         return SK_CPU_SSE_LEVEL_SSE2;
     } else {
         return 0;
     }
 }
 
 /* Verify that the requested SIMD level is supported in the build.
@@ skipping 104 matching lines @@
 };
 
 SkBlitRow::Proc SkBlitRow::PlatformProcs565(unsigned flags) {
     if (supports_simd(SK_CPU_SSE_LEVEL_SSE2)) {
         return platform_16_procs[flags];
     } else {
         return NULL;
     }
 }
 
-static SkBlitRow::Proc32 platform_32_procs[] = {
+static SkBlitRow::Proc32 platform_32_procs_SSE2[] = {
     NULL,                               // S32_Opaque,
     S32_Blend_BlitRow32_SSE2,           // S32_Blend,
     S32A_Opaque_BlitRow32_SSE2,         // S32A_Opaque
     S32A_Blend_BlitRow32_SSE2,          // S32A_Blend,
 };
 
+#if defined(SK_ATT_ASM_SUPPORTED)
+static SkBlitRow::Proc32 platform_32_procs_SSE4[] = {
+    NULL,                               // S32_Opaque,
+    S32_Blend_BlitRow32_SSE2,           // S32_Blend,
+    S32A_Opaque_BlitRow32_SSE4_asm,     // S32A_Opaque
+    S32A_Blend_BlitRow32_SSE2,          // S32A_Blend,
+};
+#endif
+
 SkBlitRow::Proc32 SkBlitRow::PlatformProcs32(unsigned flags) {
+#if defined(SK_ATT_ASM_SUPPORTED)
+    if (supports_simd(SK_CPU_SSE_LEVEL_SSE41)) {
+        return platform_32_procs_SSE4[flags];
+    } else
+#endif
     if (supports_simd(SK_CPU_SSE_LEVEL_SSE2)) {
-        return platform_32_procs[flags];
+        return platform_32_procs_SSE2[flags];
     } else {
         return NULL;
     }
 }
 
 SkBlitRow::ColorProc SkBlitRow::PlatformColorProc() {
     if (supports_simd(SK_CPU_SSE_LEVEL_SSE2)) {
         return Color32_SSE2;
     } else {
         return NULL;
@@ skipping 141 matching lines @@
     } else {
         return SkPlatformXfermodeFactory_impl(rec, mode);
     }
 }
 
 SkXfermodeProc SkPlatformXfermodeProcFactory(SkXfermode::Mode mode);
 
 SkXfermodeProc SkPlatformXfermodeProcFactory(SkXfermode::Mode mode) {
     return NULL;
 }