MIPS64: Add optimizations to li macro.

test/cctest/test-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 5537 matching lines @@
   struct TestCaseSubu {
     uint32_t imm;
     uint32_t expected_res;
     int32_t num_instr;
   };
 
   // We call Subu(v0, zero_reg, imm) to test cases listed below.
   // 0 - imm = expected_res
   struct TestCaseSubu tc[] = {
       //    imm, expected_res, num_instr
-      {0xffff8000, 0x00008000, 2},  // min_int16
+      {0xffff8000, 0x8000, 2},  // min_int16
       // Generates ori + addu
       // We can't have just addiu because -min_int16 > max_int16 so use
       // register. We can load min_int16 to at register with addiu and then
       // subtract at with subu, but now we use ori + addu because -min_int16 can
       // be loaded using ori.
       {0x8000, 0xffff8000, 1},  // max_int16 + 1
       // Generates addiu
       // max_int16 + 1 is not int16 but -(max_int16 + 1) is, just use addiu.
       {0xffff7fff, 0x8001, 2},  // min_int16 - 1
       // Generates ori + addu
@@ skipping 12 matching lines @@
       // We have to generate three instructions in this case.
   };
 
   size_t nr_test_cases = sizeof(tc) / sizeof(TestCaseSubu);
   for (size_t i = 0; i < nr_test_cases; ++i) {
     CHECK_EQ(tc[i].expected_res, run_Subu(tc[i].imm, tc[i].num_instr));
   }
 }
 
 #undef __