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Side by Side Diff: src/mips64/macro-assembler-mips64.h

Issue 2892163002: MIPS64: Add optimizations to li macro. (Closed)
Patch Set: Add Subu optimization Created 3 years, 7 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips64/assembler-mips64.h" 10 #include "src/mips64/assembler-mips64.h"
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73 USE_DELAY_SLOT, 73 USE_DELAY_SLOT,
74 PROTECT 74 PROTECT
75 }; 75 };
76 76
77 // Flags used for the li macro-assembler function. 77 // Flags used for the li macro-assembler function.
78 enum LiFlags { 78 enum LiFlags {
79 // If the constant value can be represented in just 16 bits, then 79 // If the constant value can be represented in just 16 bits, then
80 // optimize the li to use a single instruction, rather than lui/ori/dsll 80 // optimize the li to use a single instruction, rather than lui/ori/dsll
81 // sequence. 81 // sequence.
82 OPTIMIZE_SIZE = 0, 82 OPTIMIZE_SIZE = 0,
83 // Always use 6 instructions (lui/ori/dsll sequence), even if the constant 83 // Always use 6 instructions (lui/ori/dsll sequence) for release 2 or 4
84 // instructions for release 6 (lui/ori/dahi/dati), even if the constant
84 // could be loaded with just one, so that this value is patchable later. 85 // could be loaded with just one, so that this value is patchable later.
85 CONSTANT_SIZE = 1, 86 CONSTANT_SIZE = 1,
86 // For address loads only 4 instruction are required. Used to mark 87 // For address loads only 4 instruction are required. Used to mark
87 // constant load that will be used as address without relocation 88 // constant load that will be used as address without relocation
88 // information. It ensures predictable code size, so specific sites 89 // information. It ensures predictable code size, so specific sites
89 // in code are patchable. 90 // in code are patchable.
90 ADDRESS_LOAD = 2 91 ADDRESS_LOAD = 2
91 }; 92 };
92 93
93
94 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET }; 94 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
95 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK }; 95 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
96 enum PointersToHereCheck { 96 enum PointersToHereCheck {
97 kPointersToHereMaybeInteresting, 97 kPointersToHereMaybeInteresting,
98 kPointersToHereAreAlwaysInteresting 98 kPointersToHereAreAlwaysInteresting
99 }; 99 };
100 enum RAStatus { kRAHasNotBeenSaved, kRAHasBeenSaved }; 100 enum RAStatus { kRAHasNotBeenSaved, kRAHasBeenSaved };
101 101
102 Register GetRegisterThatIsNotOneOf(Register reg1, 102 Register GetRegisterThatIsNotOneOf(Register reg1,
103 Register reg2 = no_reg, 103 Register reg2 = no_reg,
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732 void Sd(Register rd, const MemOperand& rs); 732 void Sd(Register rd, const MemOperand& rs);
733 733
734 void Lwc1(FPURegister fd, const MemOperand& src); 734 void Lwc1(FPURegister fd, const MemOperand& src);
735 void Swc1(FPURegister fs, const MemOperand& dst); 735 void Swc1(FPURegister fs, const MemOperand& dst);
736 736
737 void Ldc1(FPURegister fd, const MemOperand& src); 737 void Ldc1(FPURegister fd, const MemOperand& src);
738 void Sdc1(FPURegister fs, const MemOperand& dst); 738 void Sdc1(FPURegister fs, const MemOperand& dst);
739 739
740 // Load int32 in the rd register. 740 // Load int32 in the rd register.
741 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE); 741 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
742 inline bool LiLower32BitHelper(Register rd, Operand j); 742 inline void LiLower32BitHelper(Register rd, Operand j);
743 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) { 743 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) {
744 li(rd, Operand(j), mode); 744 li(rd, Operand(j), mode);
745 } 745 }
746 void li(Register dst, Handle<Object> value, LiFlags mode = OPTIMIZE_SIZE); 746 void li(Register dst, Handle<Object> value, LiFlags mode = OPTIMIZE_SIZE);
747 747
748 // Push multiple registers on the stack. 748 // Push multiple registers on the stack.
749 // Registers are saved in numerical order, with higher numbered registers 749 // Registers are saved in numerical order, with higher numbered registers
750 // saved in higher memory addresses. 750 // saved in higher memory addresses.
751 void MultiPush(RegList regs); 751 void MultiPush(RegList regs);
752 void MultiPushReversed(RegList regs); 752 void MultiPushReversed(RegList regs);
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1964 dd(GetLabelFunction(index)); 1964 dd(GetLabelFunction(index));
1965 } 1965 }
1966 } 1966 }
1967 1967
1968 #define ACCESS_MASM(masm) masm-> 1968 #define ACCESS_MASM(masm) masm->
1969 1969
1970 } // namespace internal 1970 } // namespace internal
1971 } // namespace v8 1971 } // namespace v8
1972 1972
1973 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 1973 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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