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Issue 288853003: Allow div and cmp to work in uint32 mode (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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925 } 925 }
926 926
927 927
928 void Assembler::idiv(Register src) { 928 void Assembler::idiv(Register src) {
929 EnsureSpace ensure_space(this); 929 EnsureSpace ensure_space(this);
930 EMIT(0xF7); 930 EMIT(0xF7);
931 EMIT(0xF8 | src.code()); 931 EMIT(0xF8 | src.code());
932 } 932 }
933 933
934 934
935 void Assembler::div(Register src) {
936 EnsureSpace ensure_space(this);
937 EMIT(0xF7);
938 EMIT(0xF0 | src.code());
939 }
940
941
935 void Assembler::imul(Register reg) { 942 void Assembler::imul(Register reg) {
936 EnsureSpace ensure_space(this); 943 EnsureSpace ensure_space(this);
937 EMIT(0xF7); 944 EMIT(0xF7);
938 EMIT(0xE8 | reg.code()); 945 EMIT(0xE8 | reg.code());
939 } 946 }
940 947
941 948
942 void Assembler::imul(Register dst, const Operand& src) { 949 void Assembler::imul(Register dst, const Operand& src) {
943 EnsureSpace ensure_space(this); 950 EnsureSpace ensure_space(this);
944 EMIT(0x0F); 951 EMIT(0x0F);
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2695 fprintf(coverage_log, "%s\n", file_line); 2702 fprintf(coverage_log, "%s\n", file_line);
2696 fflush(coverage_log); 2703 fflush(coverage_log);
2697 } 2704 }
2698 } 2705 }
2699 2706
2700 #endif 2707 #endif
2701 2708
2702 } } // namespace v8::internal 2709 } } // namespace v8::internal
2703 2710
2704 #endif // V8_TARGET_ARCH_IA32 2711 #endif // V8_TARGET_ARCH_IA32
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