| Index: src/compiler/arm/code-generator-arm.cc
|
| diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
|
| index 953b6a15ea4b769782356a4b6a0b763fb4104453..cb85d74953577dc254ccfed4bd19ba374e1deb20 100644
|
| --- a/src/compiler/arm/code-generator-arm.cc
|
| +++ b/src/compiler/arm/code-generator-arm.cc
|
| @@ -1797,14 +1797,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| __ vmvn(dst, dst);
|
| break;
|
| }
|
| - case kArmI32x4LtS: {
|
| - __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI32x4GtS: {
|
| + __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI32x4LeS: {
|
| - __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI32x4GeS: {
|
| + __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmI32x4UConvertF32x4: {
|
| @@ -1836,14 +1836,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI32x4LtU: {
|
| - __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI32x4GtU: {
|
| + __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI32x4LeU: {
|
| - __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI32x4GeU: {
|
| + __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmI16x8Splat: {
|
| @@ -1937,14 +1937,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| __ vmvn(dst, dst);
|
| break;
|
| }
|
| - case kArmI16x8LtS: {
|
| - __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI16x8GtS: {
|
| + __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI16x8LeS: {
|
| - __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI16x8GeS: {
|
| + __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmI16x8UConvertI8x16Low: {
|
| @@ -1985,14 +1985,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI16x8LtU: {
|
| - __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI16x8GtU: {
|
| + __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI16x8LeU: {
|
| - __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI16x8GeU: {
|
| + __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmI8x16Splat: {
|
| @@ -2072,14 +2072,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| __ vmvn(dst, dst);
|
| break;
|
| }
|
| - case kArmI8x16LtS: {
|
| - __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI8x16GtS: {
|
| + __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI8x16LeS: {
|
| - __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI8x16GeS: {
|
| + __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmI8x16ShrU: {
|
| @@ -2110,14 +2110,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
|
| i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI8x16LtU: {
|
| - __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI8x16GtU: {
|
| + __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| - case kArmI8x16LeU: {
|
| - __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1),
|
| - i.InputSimd128Register(0));
|
| + case kArmI8x16GeU: {
|
| + __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
|
| + i.InputSimd128Register(1));
|
| break;
|
| }
|
| case kArmS128Zero: {
|
|
|