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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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198 V(Mips64F32x4Mul) \ | 198 V(Mips64F32x4Mul) \ |
199 V(Mips64F32x4Max) \ | 199 V(Mips64F32x4Max) \ |
200 V(Mips64F32x4Min) \ | 200 V(Mips64F32x4Min) \ |
201 V(Mips64F32x4Eq) \ | 201 V(Mips64F32x4Eq) \ |
202 V(Mips64F32x4Ne) \ | 202 V(Mips64F32x4Ne) \ |
203 V(Mips64F32x4Lt) \ | 203 V(Mips64F32x4Lt) \ |
204 V(Mips64F32x4Le) \ | 204 V(Mips64F32x4Le) \ |
205 V(Mips64I32x4SConvertF32x4) \ | 205 V(Mips64I32x4SConvertF32x4) \ |
206 V(Mips64I32x4UConvertF32x4) \ | 206 V(Mips64I32x4UConvertF32x4) \ |
207 V(Mips64I32x4Neg) \ | 207 V(Mips64I32x4Neg) \ |
208 V(Mips64I32x4LtS) \ | 208 V(Mips64I32x4GtS) \ |
209 V(Mips64I32x4LeS) \ | 209 V(Mips64I32x4GeS) \ |
210 V(Mips64I32x4LtU) \ | 210 V(Mips64I32x4GtU) \ |
211 V(Mips64I32x4LeU) \ | 211 V(Mips64I32x4GeU) \ |
212 V(Mips64I16x8Splat) \ | 212 V(Mips64I16x8Splat) \ |
213 V(Mips64I16x8ExtractLane) \ | 213 V(Mips64I16x8ExtractLane) \ |
214 V(Mips64I16x8ReplaceLane) \ | 214 V(Mips64I16x8ReplaceLane) \ |
215 V(Mips64I16x8Neg) \ | 215 V(Mips64I16x8Neg) \ |
216 V(Mips64I16x8Shl) \ | 216 V(Mips64I16x8Shl) \ |
217 V(Mips64I16x8ShrS) \ | 217 V(Mips64I16x8ShrS) \ |
218 V(Mips64I16x8ShrU) \ | 218 V(Mips64I16x8ShrU) \ |
219 V(Mips64I16x8Add) \ | 219 V(Mips64I16x8Add) \ |
220 V(Mips64I16x8AddSaturateS) \ | 220 V(Mips64I16x8AddSaturateS) \ |
221 V(Mips64I16x8Sub) \ | 221 V(Mips64I16x8Sub) \ |
222 V(Mips64I16x8SubSaturateS) \ | 222 V(Mips64I16x8SubSaturateS) \ |
223 V(Mips64I16x8Mul) \ | 223 V(Mips64I16x8Mul) \ |
224 V(Mips64I16x8MaxS) \ | 224 V(Mips64I16x8MaxS) \ |
225 V(Mips64I16x8MinS) \ | 225 V(Mips64I16x8MinS) \ |
226 V(Mips64I16x8Eq) \ | 226 V(Mips64I16x8Eq) \ |
227 V(Mips64I16x8Ne) \ | 227 V(Mips64I16x8Ne) \ |
228 V(Mips64I16x8LtS) \ | 228 V(Mips64I16x8GtS) \ |
229 V(Mips64I16x8LeS) \ | 229 V(Mips64I16x8GeS) \ |
230 V(Mips64I16x8AddSaturateU) \ | 230 V(Mips64I16x8AddSaturateU) \ |
231 V(Mips64I16x8SubSaturateU) \ | 231 V(Mips64I16x8SubSaturateU) \ |
232 V(Mips64I16x8MaxU) \ | 232 V(Mips64I16x8MaxU) \ |
233 V(Mips64I16x8MinU) \ | 233 V(Mips64I16x8MinU) \ |
234 V(Mips64I16x8LtU) \ | 234 V(Mips64I16x8GtU) \ |
235 V(Mips64I16x8LeU) \ | 235 V(Mips64I16x8GeU) \ |
236 V(Mips64I8x16Splat) \ | 236 V(Mips64I8x16Splat) \ |
237 V(Mips64I8x16ExtractLane) \ | 237 V(Mips64I8x16ExtractLane) \ |
238 V(Mips64I8x16ReplaceLane) \ | 238 V(Mips64I8x16ReplaceLane) \ |
239 V(Mips64I8x16Neg) \ | 239 V(Mips64I8x16Neg) \ |
240 V(Mips64I8x16Shl) \ | 240 V(Mips64I8x16Shl) \ |
241 V(Mips64I8x16ShrS) \ | 241 V(Mips64I8x16ShrS) \ |
242 V(Mips64S16x8Select) \ | 242 V(Mips64S16x8Select) \ |
243 V(Mips64S8x16Select) | 243 V(Mips64S8x16Select) |
244 | 244 |
245 // Addressing modes represent the "shape" of inputs to an instruction. | 245 // Addressing modes represent the "shape" of inputs to an instruction. |
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259 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 259 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
260 V(MRI) /* [%r0 + K] */ \ | 260 V(MRI) /* [%r0 + K] */ \ |
261 V(MRR) /* [%r0 + %r1] */ | 261 V(MRR) /* [%r0 + %r1] */ |
262 | 262 |
263 | 263 |
264 } // namespace compiler | 264 } // namespace compiler |
265 } // namespace internal | 265 } // namespace internal |
266 } // namespace v8 | 266 } // namespace v8 |
267 | 267 |
268 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 268 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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