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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 | 6 |
7 #include "src/arm/macro-assembler-arm.h" | 7 #include "src/arm/macro-assembler-arm.h" |
8 #include "src/assembler-inl.h" | 8 #include "src/assembler-inl.h" |
9 #include "src/compilation-info.h" | 9 #include "src/compilation-info.h" |
10 #include "src/compiler/code-generator-impl.h" | 10 #include "src/compiler/code-generator-impl.h" |
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1790 i.InputSimd128Register(1)); | 1790 i.InputSimd128Register(1)); |
1791 break; | 1791 break; |
1792 } | 1792 } |
1793 case kArmI32x4Ne: { | 1793 case kArmI32x4Ne: { |
1794 Simd128Register dst = i.OutputSimd128Register(); | 1794 Simd128Register dst = i.OutputSimd128Register(); |
1795 __ vceq(Neon32, dst, i.InputSimd128Register(0), | 1795 __ vceq(Neon32, dst, i.InputSimd128Register(0), |
1796 i.InputSimd128Register(1)); | 1796 i.InputSimd128Register(1)); |
1797 __ vmvn(dst, dst); | 1797 __ vmvn(dst, dst); |
1798 break; | 1798 break; |
1799 } | 1799 } |
1800 case kArmI32x4LtS: { | 1800 case kArmI32x4GtS: { |
1801 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1801 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1802 i.InputSimd128Register(0)); | 1802 i.InputSimd128Register(1)); |
1803 break; | 1803 break; |
1804 } | 1804 } |
1805 case kArmI32x4LeS: { | 1805 case kArmI32x4GeS: { |
1806 __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1806 __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1807 i.InputSimd128Register(0)); | 1807 i.InputSimd128Register(1)); |
1808 break; | 1808 break; |
1809 } | 1809 } |
1810 case kArmI32x4UConvertF32x4: { | 1810 case kArmI32x4UConvertF32x4: { |
1811 __ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1811 __ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1812 break; | 1812 break; |
1813 } | 1813 } |
1814 case kArmI32x4UConvertI16x8Low: { | 1814 case kArmI32x4UConvertI16x8Low: { |
1815 __ vmovl(NeonU16, i.OutputSimd128Register(), | 1815 __ vmovl(NeonU16, i.OutputSimd128Register(), |
1816 i.InputSimd128Register(0).low()); | 1816 i.InputSimd128Register(0).low()); |
1817 break; | 1817 break; |
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1829 case kArmI32x4MinU: { | 1829 case kArmI32x4MinU: { |
1830 __ vmin(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1830 __ vmin(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1831 i.InputSimd128Register(1)); | 1831 i.InputSimd128Register(1)); |
1832 break; | 1832 break; |
1833 } | 1833 } |
1834 case kArmI32x4MaxU: { | 1834 case kArmI32x4MaxU: { |
1835 __ vmax(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1835 __ vmax(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1836 i.InputSimd128Register(1)); | 1836 i.InputSimd128Register(1)); |
1837 break; | 1837 break; |
1838 } | 1838 } |
1839 case kArmI32x4LtU: { | 1839 case kArmI32x4GtU: { |
1840 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1840 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1841 i.InputSimd128Register(0)); | 1841 i.InputSimd128Register(1)); |
1842 break; | 1842 break; |
1843 } | 1843 } |
1844 case kArmI32x4LeU: { | 1844 case kArmI32x4GeU: { |
1845 __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1845 __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1846 i.InputSimd128Register(0)); | 1846 i.InputSimd128Register(1)); |
1847 break; | 1847 break; |
1848 } | 1848 } |
1849 case kArmI16x8Splat: { | 1849 case kArmI16x8Splat: { |
1850 __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0)); | 1850 __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0)); |
1851 break; | 1851 break; |
1852 } | 1852 } |
1853 case kArmI16x8ExtractLane: { | 1853 case kArmI16x8ExtractLane: { |
1854 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS16, | 1854 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS16, |
1855 i.InputInt8(1)); | 1855 i.InputInt8(1)); |
1856 break; | 1856 break; |
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1930 i.InputSimd128Register(1)); | 1930 i.InputSimd128Register(1)); |
1931 break; | 1931 break; |
1932 } | 1932 } |
1933 case kArmI16x8Ne: { | 1933 case kArmI16x8Ne: { |
1934 Simd128Register dst = i.OutputSimd128Register(); | 1934 Simd128Register dst = i.OutputSimd128Register(); |
1935 __ vceq(Neon16, dst, i.InputSimd128Register(0), | 1935 __ vceq(Neon16, dst, i.InputSimd128Register(0), |
1936 i.InputSimd128Register(1)); | 1936 i.InputSimd128Register(1)); |
1937 __ vmvn(dst, dst); | 1937 __ vmvn(dst, dst); |
1938 break; | 1938 break; |
1939 } | 1939 } |
1940 case kArmI16x8LtS: { | 1940 case kArmI16x8GtS: { |
1941 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1941 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1942 i.InputSimd128Register(0)); | 1942 i.InputSimd128Register(1)); |
1943 break; | 1943 break; |
1944 } | 1944 } |
1945 case kArmI16x8LeS: { | 1945 case kArmI16x8GeS: { |
1946 __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1946 __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1947 i.InputSimd128Register(0)); | 1947 i.InputSimd128Register(1)); |
1948 break; | 1948 break; |
1949 } | 1949 } |
1950 case kArmI16x8UConvertI8x16Low: { | 1950 case kArmI16x8UConvertI8x16Low: { |
1951 __ vmovl(NeonU8, i.OutputSimd128Register(), | 1951 __ vmovl(NeonU8, i.OutputSimd128Register(), |
1952 i.InputSimd128Register(0).low()); | 1952 i.InputSimd128Register(0).low()); |
1953 break; | 1953 break; |
1954 } | 1954 } |
1955 case kArmI16x8UConvertI8x16High: { | 1955 case kArmI16x8UConvertI8x16High: { |
1956 __ vmovl(NeonU8, i.OutputSimd128Register(), | 1956 __ vmovl(NeonU8, i.OutputSimd128Register(), |
1957 i.InputSimd128Register(0).high()); | 1957 i.InputSimd128Register(0).high()); |
(...skipping 20 matching lines...) Expand all Loading... |
1978 case kArmI16x8MinU: { | 1978 case kArmI16x8MinU: { |
1979 __ vmin(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1979 __ vmin(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1980 i.InputSimd128Register(1)); | 1980 i.InputSimd128Register(1)); |
1981 break; | 1981 break; |
1982 } | 1982 } |
1983 case kArmI16x8MaxU: { | 1983 case kArmI16x8MaxU: { |
1984 __ vmax(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1984 __ vmax(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1985 i.InputSimd128Register(1)); | 1985 i.InputSimd128Register(1)); |
1986 break; | 1986 break; |
1987 } | 1987 } |
1988 case kArmI16x8LtU: { | 1988 case kArmI16x8GtU: { |
1989 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1989 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1990 i.InputSimd128Register(0)); | 1990 i.InputSimd128Register(1)); |
1991 break; | 1991 break; |
1992 } | 1992 } |
1993 case kArmI16x8LeU: { | 1993 case kArmI16x8GeU: { |
1994 __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1994 __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1995 i.InputSimd128Register(0)); | 1995 i.InputSimd128Register(1)); |
1996 break; | 1996 break; |
1997 } | 1997 } |
1998 case kArmI8x16Splat: { | 1998 case kArmI8x16Splat: { |
1999 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); | 1999 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); |
2000 break; | 2000 break; |
2001 } | 2001 } |
2002 case kArmI8x16ExtractLane: { | 2002 case kArmI8x16ExtractLane: { |
2003 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS8, | 2003 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS8, |
2004 i.InputInt8(1)); | 2004 i.InputInt8(1)); |
2005 break; | 2005 break; |
(...skipping 59 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2065 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 2065 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2066 i.InputSimd128Register(1)); | 2066 i.InputSimd128Register(1)); |
2067 break; | 2067 break; |
2068 } | 2068 } |
2069 case kArmI8x16Ne: { | 2069 case kArmI8x16Ne: { |
2070 Simd128Register dst = i.OutputSimd128Register(); | 2070 Simd128Register dst = i.OutputSimd128Register(); |
2071 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); | 2071 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); |
2072 __ vmvn(dst, dst); | 2072 __ vmvn(dst, dst); |
2073 break; | 2073 break; |
2074 } | 2074 } |
2075 case kArmI8x16LtS: { | 2075 case kArmI8x16GtS: { |
2076 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 2076 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2077 i.InputSimd128Register(0)); | 2077 i.InputSimd128Register(1)); |
2078 break; | 2078 break; |
2079 } | 2079 } |
2080 case kArmI8x16LeS: { | 2080 case kArmI8x16GeS: { |
2081 __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 2081 __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2082 i.InputSimd128Register(0)); | 2082 i.InputSimd128Register(1)); |
2083 break; | 2083 break; |
2084 } | 2084 } |
2085 case kArmI8x16ShrU: { | 2085 case kArmI8x16ShrU: { |
2086 __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 2086 __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2087 i.InputInt3(1)); | 2087 i.InputInt3(1)); |
2088 break; | 2088 break; |
2089 } | 2089 } |
2090 case kArmI8x16UConvertI16x8: | 2090 case kArmI8x16UConvertI16x8: |
2091 ASSEMBLE_NEON_NARROWING_OP(NeonU8); | 2091 ASSEMBLE_NEON_NARROWING_OP(NeonU8); |
2092 break; | 2092 break; |
(...skipping 10 matching lines...) Expand all Loading... |
2103 case kArmI8x16MinU: { | 2103 case kArmI8x16MinU: { |
2104 __ vmin(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 2104 __ vmin(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2105 i.InputSimd128Register(1)); | 2105 i.InputSimd128Register(1)); |
2106 break; | 2106 break; |
2107 } | 2107 } |
2108 case kArmI8x16MaxU: { | 2108 case kArmI8x16MaxU: { |
2109 __ vmax(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 2109 __ vmax(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2110 i.InputSimd128Register(1)); | 2110 i.InputSimd128Register(1)); |
2111 break; | 2111 break; |
2112 } | 2112 } |
2113 case kArmI8x16LtU: { | 2113 case kArmI8x16GtU: { |
2114 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 2114 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2115 i.InputSimd128Register(0)); | 2115 i.InputSimd128Register(1)); |
2116 break; | 2116 break; |
2117 } | 2117 } |
2118 case kArmI8x16LeU: { | 2118 case kArmI8x16GeU: { |
2119 __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 2119 __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
2120 i.InputSimd128Register(0)); | 2120 i.InputSimd128Register(1)); |
2121 break; | 2121 break; |
2122 } | 2122 } |
2123 case kArmS128Zero: { | 2123 case kArmS128Zero: { |
2124 __ veor(i.OutputSimd128Register(), i.OutputSimd128Register(), | 2124 __ veor(i.OutputSimd128Register(), i.OutputSimd128Register(), |
2125 i.OutputSimd128Register()); | 2125 i.OutputSimd128Register()); |
2126 break; | 2126 break; |
2127 } | 2127 } |
2128 case kArmS128And: { | 2128 case kArmS128And: { |
2129 __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0), | 2129 __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0), |
2130 i.InputSimd128Register(1)); | 2130 i.InputSimd128Register(1)); |
(...skipping 1115 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3246 padding_size -= v8::internal::Assembler::kInstrSize; | 3246 padding_size -= v8::internal::Assembler::kInstrSize; |
3247 } | 3247 } |
3248 } | 3248 } |
3249 } | 3249 } |
3250 | 3250 |
3251 #undef __ | 3251 #undef __ |
3252 | 3252 |
3253 } // namespace compiler | 3253 } // namespace compiler |
3254 } // namespace internal | 3254 } // namespace internal |
3255 } // namespace v8 | 3255 } // namespace v8 |
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