[arm] Print address for load literal instructions.

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1375 matching lines @@
     COMPARE(pld(MemOperand(r1, 0)),
             "f5d1f000       pld [r1]");
     COMPARE(pld(MemOperand(r2, 128)),
             "f5d2f080       pld [r2, #+128]");
   }
 
   VERIFY_RUN();
 }
 
 
+static void TestLoadLiteral(byte* buffer, Assembler* assm, bool* failure,
+                            int offset) {
+  int pc_offset = assm->pc_offset();
+  byte *progcounter = &buffer[pc_offset];
+  assm->ldr(r0, MemOperand(pc, offset));
+
+  const char *expected_string_template =
+    (offset >= 0) ?
+    "e59f0%03x       ldr r0, [pc, #+%d] (addr %p)" :
+    "e51f0%03x       ldr r0, [pc, #%d] (addr %p)";
+  char expected_string[80];
+  snprintf(expected_string, sizeof(expected_string), expected_string_template,
+           abs(offset), offset,
+           progcounter + Instruction::kPCReadOffset + offset);
+  if (!DisassembleAndCompare(progcounter, expected_string)) *failure = true;
+}
+
+
+TEST(LoadLiteral) {
+  SET_UP();
+
+  TestLoadLiteral(buffer, &assm, &failure, 0);
+  TestLoadLiteral(buffer, &assm, &failure, 1);
+  TestLoadLiteral(buffer, &assm, &failure, 4);
+  TestLoadLiteral(buffer, &assm, &failure, 4095);
+  TestLoadLiteral(buffer, &assm, &failure, -1);
+  TestLoadLiteral(buffer, &assm, &failure, -4);
+  TestLoadLiteral(buffer, &assm, &failure, -4095);
+
+  VERIFY_RUN();
+}
+
+
 TEST(Barrier) {
   SET_UP();
 
   if (CpuFeatures::IsSupported(ARMv7)) {
     CpuFeatureScope scope(&assm, ARMv7);
 
     COMPARE(dmb(OSHLD),
             "f57ff051       dmb oshld");
     COMPARE(dmb(OSHST),
             "f57ff052       dmb oshst");
@@ skipping 57 matching lines @@
 
   COMPARE(ldrexb(r0, r1), "e1d10f9f       ldrexb r0, [r1]");
   COMPARE(strexb(r0, r1, r2), "e1c20f91       strexb r0, r1, [r2]");
   COMPARE(ldrexh(r0, r1), "e1f10f9f       ldrexh r0, [r1]");
   COMPARE(strexh(r0, r1, r2), "e1e20f91       strexh r0, r1, [r2]");
   COMPARE(ldrex(r0, r1), "e1910f9f       ldrex r0, [r1]");
   COMPARE(strex(r0, r1, r2), "e1820f91       strex r0, r1, [r2]");
 
   VERIFY_RUN();
 }