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Issue 286193004: ARM64 simulator fix for EXTR (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 7 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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4886 4886
4887 TEST(extr) { 4887 TEST(extr) {
4888 INIT_V8(); 4888 INIT_V8();
4889 SETUP(); 4889 SETUP();
4890 4890
4891 START(); 4891 START();
4892 __ Mov(x1, 0x0123456789abcdefL); 4892 __ Mov(x1, 0x0123456789abcdefL);
4893 __ Mov(x2, 0xfedcba9876543210L); 4893 __ Mov(x2, 0xfedcba9876543210L);
4894 4894
4895 __ Extr(w10, w1, w2, 0); 4895 __ Extr(w10, w1, w2, 0);
4896 __ Extr(w11, w1, w2, 1); 4896 __ Extr(x11, x1, x2, 0);
4897 __ Extr(x12, x2, x1, 2); 4897 __ Extr(w12, w1, w2, 1);
4898 __ Extr(x13, x2, x1, 2);
4898 4899
4899 __ Ror(w13, w1, 0); 4900 __ Ror(w20, w1, 0);
4900 __ Ror(w14, w2, 17); 4901 __ Ror(x21, x1, 0);
4901 __ Ror(w15, w1, 31); 4902 __ Ror(w22, w2, 17);
4902 __ Ror(x18, x2, 1); 4903 __ Ror(w23, w1, 31);
4903 __ Ror(x19, x1, 63); 4904 __ Ror(x24, x2, 1);
4905 __ Ror(x25, x1, 63);
4904 END(); 4906 END();
4905 4907
4906 RUN(); 4908 RUN();
4907 4909
4908 ASSERT_EQUAL_64(0x76543210, x10); 4910 ASSERT_EQUAL_64(0x76543210, x10);
4909 ASSERT_EQUAL_64(0xbb2a1908, x11); 4911 ASSERT_EQUAL_64(0xfedcba9876543210L, x11);
4910 ASSERT_EQUAL_64(0x0048d159e26af37bUL, x12); 4912 ASSERT_EQUAL_64(0xbb2a1908, x12);
4911 ASSERT_EQUAL_64(0x89abcdef, x13); 4913 ASSERT_EQUAL_64(0x0048d159e26af37bUL, x13);
4912 ASSERT_EQUAL_64(0x19083b2a, x14); 4914 ASSERT_EQUAL_64(0x89abcdef, x20);
4913 ASSERT_EQUAL_64(0x13579bdf, x15); 4915 ASSERT_EQUAL_64(0x0123456789abcdefL, x21);
4914 ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x18); 4916 ASSERT_EQUAL_64(0x19083b2a, x22);
4915 ASSERT_EQUAL_64(0x02468acf13579bdeUL, x19); 4917 ASSERT_EQUAL_64(0x13579bdf, x23);
4918 ASSERT_EQUAL_64(0x7f6e5d4c3b2a1908UL, x24);
4919 ASSERT_EQUAL_64(0x02468acf13579bdeUL, x25);
4916 4920
4917 TEARDOWN(); 4921 TEARDOWN();
4918 } 4922 }
4919 4923
4920 4924
4921 TEST(fmov_imm) { 4925 TEST(fmov_imm) {
4922 INIT_V8(); 4926 INIT_V8();
4923 SETUP(); 4927 SETUP();
4924 4928
4925 START(); 4929 START();
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10977 if (RelocInfo::IsVeneerPool(info->rmode())) { 10981 if (RelocInfo::IsVeneerPool(info->rmode())) {
10978 ASSERT(info->data() == veneer_pool_size); 10982 ASSERT(info->data() == veneer_pool_size);
10979 ++pool_count; 10983 ++pool_count;
10980 } 10984 }
10981 } 10985 }
10982 10986
10983 ASSERT(pool_count == 2); 10987 ASSERT(pool_count == 2);
10984 10988
10985 TEARDOWN(); 10989 TEARDOWN();
10986 } 10990 }
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