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Issue 286193004: ARM64 simulator fix for EXTR (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 7 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <stdlib.h> 5 #include <stdlib.h>
6 #include <cmath> 6 #include <cmath>
7 #include <cstdarg> 7 #include <cstdarg>
8 #include "v8.h" 8 #include "v8.h"
9 9
10 #if V8_TARGET_ARCH_ARM64 10 #if V8_TARGET_ARCH_ARM64
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2096 result = signbits | (result & mask) | (dst & ~mask); 2096 result = signbits | (result & mask) | (dst & ~mask);
2097 2097
2098 set_reg(reg_size, instr->Rd(), result); 2098 set_reg(reg_size, instr->Rd(), result);
2099 } 2099 }
2100 2100
2101 2101
2102 void Simulator::VisitExtract(Instruction* instr) { 2102 void Simulator::VisitExtract(Instruction* instr) {
2103 unsigned lsb = instr->ImmS(); 2103 unsigned lsb = instr->ImmS();
2104 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits 2104 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
2105 : kWRegSizeInBits; 2105 : kWRegSizeInBits;
2106 set_reg(reg_size, 2106 uint64_t result = reg(reg_size, instr->Rm());
2107 instr->Rd(), 2107 if (lsb) {
2108 (static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb) | 2108 result = (result >> lsb) | (reg(reg_size, instr->Rn()) << (reg_size - lsb));
2109 (reg(reg_size, instr->Rn()) << (reg_size - lsb))); 2109 }
2110
2111 set_reg(reg_size, instr->Rd(), result);
2110 } 2112 }
2111 2113
2112 2114
2113 void Simulator::VisitFPImmediate(Instruction* instr) { 2115 void Simulator::VisitFPImmediate(Instruction* instr) {
2114 AssertSupportedFPCR(); 2116 AssertSupportedFPCR();
2115 2117
2116 unsigned dest = instr->Rd(); 2118 unsigned dest = instr->Rd();
2117 switch (instr->Mask(FPImmediateMask)) { 2119 switch (instr->Mask(FPImmediateMask)) {
2118 case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break; 2120 case FMOV_s_imm: set_sreg(dest, instr->ImmFP32()); break;
2119 case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break; 2121 case FMOV_d_imm: set_dreg(dest, instr->ImmFP64()); break;
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3724 3726
3725 delete[] format; 3727 delete[] format;
3726 } 3728 }
3727 3729
3728 3730
3729 #endif // USE_SIMULATOR 3731 #endif // USE_SIMULATOR
3730 3732
3731 } } // namespace v8::internal 3733 } } // namespace v8::internal
3732 3734
3733 #endif // V8_TARGET_ARCH_ARM64 3735 #endif // V8_TARGET_ARCH_ARM64
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