[ARM] Implement irregular vector shuffles for SIMD.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 2565 matching lines @@
   ArchOpcode opcode;
 };
 
 static const ShuffleEntry<4> arch_s32x4_shuffles[] = {
     {{0, 4, 1, 5}, kArmS32x4ZipLeft},
     {{2, 6, 3, 7}, kArmS32x4ZipRight},
     {{0, 2, 4, 6}, kArmS32x4UnzipLeft},
     {{1, 3, 5, 7}, kArmS32x4UnzipRight},
     {{0, 4, 2, 6}, kArmS32x4TransposeLeft},
     {{1, 5, 3, 7}, kArmS32x4TransposeRight},
-    {{1, 0, 3, 2}, kArmS32x2Reverse},
-};
+    {{1, 0, 3, 2}, kArmS32x2Reverse}};
 
 static const ShuffleEntry<8> arch_s16x8_shuffles[] = {
     {{0, 8, 1, 9, 2, 10, 3, 11}, kArmS16x8ZipLeft},
     {{4, 12, 5, 13, 6, 14, 7, 15}, kArmS16x8ZipRight},
     {{0, 2, 4, 6, 8, 10, 12, 14}, kArmS16x8UnzipLeft},
     {{1, 3, 5, 7, 9, 11, 13, 15}, kArmS16x8UnzipRight},
     {{0, 8, 2, 10, 4, 12, 6, 14}, kArmS16x8TransposeLeft},
     {{1, 9, 3, 11, 5, 13, 7, 15}, kArmS16x8TransposeRight},
     {{3, 2, 1, 0, 7, 6, 5, 4}, kArmS16x4Reverse},
-    {{1, 0, 3, 2, 5, 4, 7, 6}, kArmS16x2Reverse},
-};
+    {{1, 0, 3, 2, 5, 4, 7, 6}, kArmS16x2Reverse}};
 
 static const ShuffleEntry<16> arch_s8x16_shuffles[] = {
     {{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23},
      kArmS8x16ZipLeft},
     {{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31},
      kArmS8x16ZipRight},
     {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30},
      kArmS8x16UnzipLeft},
     {{1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31},
      kArmS8x16UnzipRight},
     {{0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30},
      kArmS8x16TransposeLeft},
     {{1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31},
      kArmS8x16TransposeRight},
     {{7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}, kArmS8x8Reverse},
     {{3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}, kArmS8x4Reverse},
-    {{1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}, kArmS8x2Reverse},
-};
+    {{1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}, kArmS8x2Reverse}};
 
 // Use a non-shuffle opcode to signal no match.
 static const ArchOpcode kNoShuffle = kArmS128Not;
 
 template <int LANES>
 ArchOpcode TryMatchArchShuffle(const uint8_t* shuffle,
                                const ShuffleEntry<LANES>* table,
                                size_t num_entries, uint8_t mask) {
   for (size_t i = 0; i < num_entries; i++) {
     const ShuffleEntry<LANES>& entry = table[i];
@@ skipping 49 matching lines @@
       node->ReplaceInput(1, node->InputAt(0));
       mask = num_lanes - 1;
     } else if (src1_is_used && !src0_is_used) {
       node->ReplaceInput(0, node->InputAt(1));
       mask = num_lanes - 1;
     }
   }
   return mask;
 }
 
+int32_t Pack4Lanes(const uint8_t* shuffle, uint8_t mask) {
+  int32_t result = 0;
+  for (int i = 3; i >= 0; i--) {
+    result <<= 8;
+    result |= shuffle[i] & mask;
+  }
+  return result;
+}
+
+void ArrangeShuffleTable(ArmOperandGenerator* g, Node* input0, Node* input1,
+                         InstructionOperand* src0, InstructionOperand* src1) {
+  if (input0 == input1) {
+    // Unary, any q-register can be the table.
+    *src0 = *src1 = g->UseRegister(input0);
+  } else {
+    // Binary, table registers must be consecutive.
+    *src0 = g->UseFixed(input0, q0);
+    *src1 = g->UseFixed(input1, q1);
+  }
+}
+
 }  // namespace
 
 void InstructionSelector::VisitS32x4Shuffle(Node* node) {
   const uint8_t* shuffle = OpParameter<uint8_t*>(node);
   uint8_t mask = CanonicalizeShuffle(this, node, 4);
   ArchOpcode opcode = TryMatchArchShuffle<4>(
       shuffle, arch_s32x4_shuffles, arraysize(arch_s32x4_shuffles), mask);
   if (opcode != kNoShuffle) {
     VisitRRRShuffle(this, opcode, node);
     return;
   }
   ArmOperandGenerator g(this);
   uint8_t lanes = TryMatchConcat<4>(shuffle, mask);
   if (lanes != 0) {
     Emit(kArmS8x16Concat, g.DefineAsRegister(node),
          g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
          g.UseImmediate(lanes * 4));
     return;
   }
-  // TODO(bbudge) vtbl to handle all other shuffles.
+  Emit(kArmS32x4Shuffle, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
+       g.UseImmediate(Pack4Lanes(shuffle, mask)));
 }
 
 void InstructionSelector::VisitS16x8Shuffle(Node* node) {
   const uint8_t* shuffle = OpParameter<uint8_t*>(node);
   uint8_t mask = CanonicalizeShuffle(this, node, 8);
   ArchOpcode opcode = TryMatchArchShuffle<8>(
       shuffle, arch_s16x8_shuffles, arraysize(arch_s16x8_shuffles), mask);
   if (opcode != kNoShuffle) {
     VisitRRRShuffle(this, opcode, node);
     return;
   }
   ArmOperandGenerator g(this);
+  Node* input0 = node->InputAt(0);
+  Node* input1 = node->InputAt(1);
   uint8_t lanes = TryMatchConcat<8>(shuffle, mask);
   if (lanes != 0) {
-    Emit(kArmS8x16Concat, g.DefineAsRegister(node),
-         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
-         g.UseImmediate(lanes * 2));
+    Emit(kArmS8x16Concat, g.DefineAsRegister(node), g.UseRegister(input0),
+         g.UseRegister(input1), g.UseImmediate(lanes * 2));
+    return;
   }
-  // TODO(bbudge) vtbl to handle all other shuffles.
+  // Code generator uses vtbl, arrange sources to form a valid lookup table.
+  InstructionOperand src0, src1;
+  ArrangeShuffleTable(&g, input0, input1, &src0, &src1);
+  Emit(kArmS16x8Shuffle, g.DefineAsRegister(node), src0, src1,
+       g.UseImmediate(Pack4Lanes(shuffle, mask)),
+       g.UseImmediate(Pack4Lanes(shuffle + 4, mask)));
 }
 
 void InstructionSelector::VisitS8x16Shuffle(Node* node) {
   const uint8_t* shuffle = OpParameter<uint8_t*>(node);
   uint8_t mask = CanonicalizeShuffle(this, node, 16);
   ArchOpcode opcode = TryMatchArchShuffle<16>(
       shuffle, arch_s8x16_shuffles, arraysize(arch_s8x16_shuffles), mask);
   if (opcode != kNoShuffle) {
     VisitRRRShuffle(this, opcode, node);
     return;
   }
   ArmOperandGenerator g(this);
+  Node* input0 = node->InputAt(0);
+  Node* input1 = node->InputAt(1);
   uint8_t lanes = TryMatchConcat<16>(shuffle, mask);
   if (lanes != 0) {
-    Emit(kArmS8x16Concat, g.DefineAsRegister(node),
-         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
-         g.UseImmediate(lanes));
+    Emit(kArmS8x16Concat, g.DefineAsRegister(node), g.UseRegister(input0),
+         g.UseRegister(input1), g.UseImmediate(lanes));
+    return;
   }
-  // TODO(bbudge) vtbl to handle all other shuffles.
+  // Code generator uses vtbl, arrange sources to form a valid lookup table.
+  InstructionOperand src0, src1;
+  ArrangeShuffleTable(&g, input0, input1, &src0, &src1);
+  Emit(kArmS8x16Shuffle, g.DefineAsRegister(node), src0, src1,
+       g.UseImmediate(Pack4Lanes(shuffle, mask)),
+       g.UseImmediate(Pack4Lanes(shuffle + 4, mask)),
+       g.UseImmediate(Pack4Lanes(shuffle + 8, mask)),
+       g.UseImmediate(Pack4Lanes(shuffle + 12, mask)));
 }
 
 void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
   UNREACHABLE();
 }
 
 void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   UNREACHABLE();
 }
 
@@ skipping 30 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8