[wasm] Implement Generic S128 Load/Store, logical ops and Horizontal add

src/compiler/x64/code-generator-x64.cc

Index: src/compiler/x64/code-generator-x64.cc
diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc
index 72dc78f24b53cf3c1a30d95bb3b85b071dc38873..a0f3428e433468e14cd7867afd49b1dd1990d388 100644
--- a/src/compiler/x64/code-generator-x64.cc
+++ b/src/compiler/x64/code-generator-x64.cc
@@ -2006,6 +2006,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
         __ Movsd(operand, i.InputDoubleRegister(index));
       }
       break;
+    case kX64Movdqu: {
+      CpuFeatureScope sse_scope(masm(), SSSE3);
+      EmitOOLTrapIfNeeded(zone(), this, opcode, instr->InputCount(), i,
+                          __ pc_offset());
+      if (instr->HasOutput()) {
+        __ movdqu(i.OutputSimd128Register(), i.MemoryOperand());
+      } else {
+        size_t index = 0;
+        Operand operand = i.MemoryOperand(&index);
+        __ movdqu(operand, i.InputSimd128Register(index));
+      }
+      break;
+    }
     case kX64BitcastFI:
       if (instr->InputAt(0)->IsFPStackSlot()) {
         __ movl(i.OutputRegister(), i.InputOperand(0));
@@ -2187,6 +2200,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ paddd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
+    case kX64I32x4AddHoriz: {
+      CpuFeatureScope sse_scope(masm(), SSSE3);
+      __ phaddd(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
     case kX64I32x4Sub: {
       __ psubd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
@@ -2276,6 +2294,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ paddsw(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
+    case kX64I16x8AddHoriz: {
+      CpuFeatureScope sse_scope(masm(), SSSE3);
+      __ phaddw(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
     case kX64I16x8Sub: {
       __ psubw(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
@@ -2410,6 +2433,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ pmaxub(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
+    case kX64S128And: {
+      __ pand(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64S128Or: {
+      __ por(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64S128Xor: {
+      __ pxor(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      break;
+    }
+    case kX64S128Not: {
+      XMMRegister dst = i.OutputSimd128Register();
+      __ pxor(dst, dst);

[zvi, 2017/04/27 15:29:14]

You can probably do without this XOR as starting from Sandybridge, the processor
recognizes the all-one idiom and breaks dependencies on earlier defs to the
register.

Here is what the Optimization Reference Manual has to say:
There is another dependency breaking idiom - the "ones idiom".
• CMPEQ XMM1, XMM1; "ones idiom" set all elements to all "ones"
In this case, the micro-op must execute, however, since it is known that
regardless of the input data the
output data is always "all ones" the micro-op dependency upon its sources does
not exist as with the zero
idiom and it can execute as soon as it finds a free execution port.

[gdeepti, 2017/04/27 16:30:38]

Removed xor, thanks for the pointer to the Optimization Reference Manual. 

+      __ pcmpeqd(dst, dst);
+      __ pxor(dst, i.InputSimd128Register(1));
+      break;
+    }
     case kX64S128Select: {
       // Mask used here is stored in dst.
       XMMRegister dst = i.OutputSimd128Register();