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Side by Side Diff: src/compiler/instruction-selector.cc

Issue 2847663005: [WASM SIMD] Replace primitive shuffles with general Shuffle. (Closed)
Patch Set: Remove stray wasm opcode. Created 3 years, 7 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/instruction-selector.h" 5 #include "src/compiler/instruction-selector.h"
6 6
7 #include <limits> 7 #include <limits>
8 8
9 #include "src/assembler-inl.h" 9 #include "src/assembler-inl.h"
10 #include "src/base/adapters.h" 10 #include "src/base/adapters.h"
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1698 case IrOpcode::kS128Zero: 1698 case IrOpcode::kS128Zero:
1699 return MarkAsSimd128(node), VisitS128Zero(node); 1699 return MarkAsSimd128(node), VisitS128Zero(node);
1700 case IrOpcode::kS128And: 1700 case IrOpcode::kS128And:
1701 return MarkAsSimd128(node), VisitS128And(node); 1701 return MarkAsSimd128(node), VisitS128And(node);
1702 case IrOpcode::kS128Or: 1702 case IrOpcode::kS128Or:
1703 return MarkAsSimd128(node), VisitS128Or(node); 1703 return MarkAsSimd128(node), VisitS128Or(node);
1704 case IrOpcode::kS128Xor: 1704 case IrOpcode::kS128Xor:
1705 return MarkAsSimd128(node), VisitS128Xor(node); 1705 return MarkAsSimd128(node), VisitS128Xor(node);
1706 case IrOpcode::kS128Not: 1706 case IrOpcode::kS128Not:
1707 return MarkAsSimd128(node), VisitS128Not(node); 1707 return MarkAsSimd128(node), VisitS128Not(node);
1708 case IrOpcode::kS32x4ZipLeft: 1708 case IrOpcode::kS32x4Shuffle:
1709 return MarkAsSimd128(node), VisitS32x4ZipLeft(node); 1709 return MarkAsSimd128(node), VisitS32x4Shuffle(node);
1710 case IrOpcode::kS32x4ZipRight:
1711 return MarkAsSimd128(node), VisitS32x4ZipRight(node);
1712 case IrOpcode::kS32x4UnzipLeft:
1713 return MarkAsSimd128(node), VisitS32x4UnzipLeft(node);
1714 case IrOpcode::kS32x4UnzipRight:
1715 return MarkAsSimd128(node), VisitS32x4UnzipRight(node);
1716 case IrOpcode::kS32x4TransposeLeft:
1717 return MarkAsSimd128(node), VisitS32x4TransposeLeft(node);
1718 case IrOpcode::kS32x4TransposeRight:
1719 return MarkAsSimd128(node), VisitS32x4TransposeRight(node);
1720 case IrOpcode::kS32x4Select: 1710 case IrOpcode::kS32x4Select:
1721 return MarkAsSimd128(node), VisitS32x4Select(node); 1711 return MarkAsSimd128(node), VisitS32x4Select(node);
1722 case IrOpcode::kS16x8ZipLeft: 1712 case IrOpcode::kS16x8Shuffle:
1723 return MarkAsSimd128(node), VisitS16x8ZipLeft(node); 1713 return MarkAsSimd128(node), VisitS16x8Shuffle(node);
1724 case IrOpcode::kS16x8ZipRight:
1725 return MarkAsSimd128(node), VisitS16x8ZipRight(node);
1726 case IrOpcode::kS16x8UnzipLeft:
1727 return MarkAsSimd128(node), VisitS16x8UnzipLeft(node);
1728 case IrOpcode::kS16x8UnzipRight:
1729 return MarkAsSimd128(node), VisitS16x8UnzipRight(node);
1730 case IrOpcode::kS16x8TransposeLeft:
1731 return MarkAsSimd128(node), VisitS16x8TransposeLeft(node);
1732 case IrOpcode::kS16x8TransposeRight:
1733 return MarkAsSimd128(node), VisitS16x8TransposeRight(node);
1734 case IrOpcode::kS16x8Select: 1714 case IrOpcode::kS16x8Select:
1735 return MarkAsSimd128(node), VisitS16x8Select(node); 1715 return MarkAsSimd128(node), VisitS16x8Select(node);
1736 case IrOpcode::kS8x16ZipLeft: 1716 case IrOpcode::kS8x16Shuffle:
1737 return MarkAsSimd128(node), VisitS8x16ZipLeft(node); 1717 return MarkAsSimd128(node), VisitS8x16Shuffle(node);
1738 case IrOpcode::kS8x16ZipRight:
1739 return MarkAsSimd128(node), VisitS8x16ZipRight(node);
1740 case IrOpcode::kS8x16UnzipLeft:
1741 return MarkAsSimd128(node), VisitS8x16UnzipLeft(node);
1742 case IrOpcode::kS8x16UnzipRight:
1743 return MarkAsSimd128(node), VisitS8x16UnzipRight(node);
1744 case IrOpcode::kS8x16TransposeLeft:
1745 return MarkAsSimd128(node), VisitS8x16TransposeLeft(node);
1746 case IrOpcode::kS8x16TransposeRight:
1747 return MarkAsSimd128(node), VisitS8x16TransposeRight(node);
1748 case IrOpcode::kS8x16Select: 1718 case IrOpcode::kS8x16Select:
1749 return MarkAsSimd128(node), VisitS8x16Select(node); 1719 return MarkAsSimd128(node), VisitS8x16Select(node);
1750 case IrOpcode::kS8x16Concat:
1751 return MarkAsSimd128(node), VisitS8x16Concat(node);
1752 case IrOpcode::kS32x2Reverse:
1753 return MarkAsSimd128(node), VisitS32x2Reverse(node);
1754 case IrOpcode::kS16x4Reverse:
1755 return MarkAsSimd128(node), VisitS16x4Reverse(node);
1756 case IrOpcode::kS16x2Reverse:
1757 return MarkAsSimd128(node), VisitS16x2Reverse(node);
1758 case IrOpcode::kS8x8Reverse:
1759 return MarkAsSimd128(node), VisitS8x8Reverse(node);
1760 case IrOpcode::kS8x4Reverse:
1761 return MarkAsSimd128(node), VisitS8x4Reverse(node);
1762 case IrOpcode::kS8x2Reverse:
1763 return MarkAsSimd128(node), VisitS8x2Reverse(node);
1764 case IrOpcode::kS1x4Zero: 1720 case IrOpcode::kS1x4Zero:
1765 return MarkAsSimd1x4(node), VisitS1x4Zero(node); 1721 return MarkAsSimd1x4(node), VisitS1x4Zero(node);
1766 case IrOpcode::kS1x4And: 1722 case IrOpcode::kS1x4And:
1767 return MarkAsSimd1x4(node), VisitS1x4And(node); 1723 return MarkAsSimd1x4(node), VisitS1x4And(node);
1768 case IrOpcode::kS1x4Or: 1724 case IrOpcode::kS1x4Or:
1769 return MarkAsSimd1x4(node), VisitS1x4Or(node); 1725 return MarkAsSimd1x4(node), VisitS1x4Or(node);
1770 case IrOpcode::kS1x4Xor: 1726 case IrOpcode::kS1x4Xor:
1771 return MarkAsSimd1x4(node), VisitS1x4Xor(node); 1727 return MarkAsSimd1x4(node), VisitS1x4Xor(node);
1772 case IrOpcode::kS1x4Not: 1728 case IrOpcode::kS1x4Not:
1773 return MarkAsSimd1x4(node), VisitS1x4Not(node); 1729 return MarkAsSimd1x4(node), VisitS1x4Not(node);
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2449 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && 2405 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
2450 // !V8_TARGET_ARCH_MIPS64 2406 // !V8_TARGET_ARCH_MIPS64
2451 2407
2452 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \ 2408 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
2453 !V8_TARGET_ARCH_MIPS64 2409 !V8_TARGET_ARCH_MIPS64
2454 void InstructionSelector::VisitS32x4Select(Node* node) { UNIMPLEMENTED(); } 2410 void InstructionSelector::VisitS32x4Select(Node* node) { UNIMPLEMENTED(); }
2455 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && 2411 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
2456 // !V8_TARGET_ARCH_MIPS64 2412 // !V8_TARGET_ARCH_MIPS64
2457 2413
2458 #if !V8_TARGET_ARCH_ARM 2414 #if !V8_TARGET_ARCH_ARM
2459 void InstructionSelector::VisitS32x4ZipLeft(Node* node) { UNIMPLEMENTED(); } 2415 void InstructionSelector::VisitS32x4Shuffle(Node* node) { UNIMPLEMENTED(); }
2460 2416
2461 void InstructionSelector::VisitS32x4ZipRight(Node* node) { UNIMPLEMENTED(); } 2417 void InstructionSelector::VisitS16x8Shuffle(Node* node) { UNIMPLEMENTED(); }
2462 2418
2463 void InstructionSelector::VisitS32x4UnzipLeft(Node* node) { UNIMPLEMENTED(); }
2464
2465 void InstructionSelector::VisitS32x4UnzipRight(Node* node) { UNIMPLEMENTED(); }
2466
2467 void InstructionSelector::VisitS32x4TransposeLeft(Node* node) {
2468 UNIMPLEMENTED();
2469 }
2470
2471 void InstructionSelector::VisitS32x4TransposeRight(Node* node) {
2472 UNIMPLEMENTED();
2473 }
2474
2475 void InstructionSelector::VisitS16x8ZipLeft(Node* node) { UNIMPLEMENTED(); }
2476
2477 void InstructionSelector::VisitS16x8ZipRight(Node* node) { UNIMPLEMENTED(); }
2478
2479 void InstructionSelector::VisitS16x8UnzipLeft(Node* node) { UNIMPLEMENTED(); }
2480
2481 void InstructionSelector::VisitS16x8UnzipRight(Node* node) { UNIMPLEMENTED(); }
2482
2483 void InstructionSelector::VisitS16x8TransposeLeft(Node* node) {
2484 UNIMPLEMENTED();
2485 }
2486
2487 void InstructionSelector::VisitS16x8TransposeRight(Node* node) {
2488 UNIMPLEMENTED();
2489 }
2490 #endif // !V8_TARGET_ARCH_ARM 2419 #endif // !V8_TARGET_ARCH_ARM
2491 2420
2492 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM 2421 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
2493 void InstructionSelector::VisitS16x8Select(Node* node) { UNIMPLEMENTED(); } 2422 void InstructionSelector::VisitS16x8Select(Node* node) { UNIMPLEMENTED(); }
2494 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM 2423 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
2495 2424
2496 #if !V8_TARGET_ARCH_ARM 2425 #if !V8_TARGET_ARCH_ARM
2497 void InstructionSelector::VisitS8x16ZipLeft(Node* node) { UNIMPLEMENTED(); } 2426 void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
2498 2427
2499 void InstructionSelector::VisitS8x16ZipRight(Node* node) { UNIMPLEMENTED(); }
2500
2501 void InstructionSelector::VisitS8x16UnzipLeft(Node* node) { UNIMPLEMENTED(); }
2502
2503 void InstructionSelector::VisitS8x16UnzipRight(Node* node) { UNIMPLEMENTED(); }
2504
2505 void InstructionSelector::VisitS8x16TransposeLeft(Node* node) {
2506 UNIMPLEMENTED();
2507 }
2508
2509 void InstructionSelector::VisitS8x16TransposeRight(Node* node) {
2510 UNIMPLEMENTED();
2511 }
2512 #endif // !V8_TARGET_ARCH_ARM 2428 #endif // !V8_TARGET_ARCH_ARM
2513 2429
2514 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM 2430 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
2515 void InstructionSelector::VisitS8x16Select(Node* node) { UNIMPLEMENTED(); } 2431 void InstructionSelector::VisitS8x16Select(Node* node) { UNIMPLEMENTED(); }
2516 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM 2432 #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
2517 2433
2518 #if !V8_TARGET_ARCH_ARM 2434 #if !V8_TARGET_ARCH_ARM
2519 void InstructionSelector::VisitS8x16Concat(Node* node) { UNIMPLEMENTED(); }
2520
2521 void InstructionSelector::VisitS32x2Reverse(Node* node) { UNIMPLEMENTED(); }
2522
2523 void InstructionSelector::VisitS16x4Reverse(Node* node) { UNIMPLEMENTED(); }
2524
2525 void InstructionSelector::VisitS16x2Reverse(Node* node) { UNIMPLEMENTED(); }
2526
2527 void InstructionSelector::VisitS8x8Reverse(Node* node) { UNIMPLEMENTED(); }
2528
2529 void InstructionSelector::VisitS8x4Reverse(Node* node) { UNIMPLEMENTED(); }
2530
2531 void InstructionSelector::VisitS8x2Reverse(Node* node) { UNIMPLEMENTED(); }
2532
2533 void InstructionSelector::VisitS1x4And(Node* node) { UNIMPLEMENTED(); } 2435 void InstructionSelector::VisitS1x4And(Node* node) { UNIMPLEMENTED(); }
2534 2436
2535 void InstructionSelector::VisitS1x4Or(Node* node) { UNIMPLEMENTED(); } 2437 void InstructionSelector::VisitS1x4Or(Node* node) { UNIMPLEMENTED(); }
2536 2438
2537 void InstructionSelector::VisitS1x4Xor(Node* node) { UNIMPLEMENTED(); } 2439 void InstructionSelector::VisitS1x4Xor(Node* node) { UNIMPLEMENTED(); }
2538 2440
2539 void InstructionSelector::VisitS1x4Not(Node* node) { UNIMPLEMENTED(); } 2441 void InstructionSelector::VisitS1x4Not(Node* node) { UNIMPLEMENTED(); }
2540 2442
2541 void InstructionSelector::VisitS1x4AnyTrue(Node* node) { UNIMPLEMENTED(); } 2443 void InstructionSelector::VisitS1x4AnyTrue(Node* node) { UNIMPLEMENTED(); }
2542 2444
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2939 return new (instruction_zone()) FrameStateDescriptor( 2841 return new (instruction_zone()) FrameStateDescriptor(
2940 instruction_zone(), state_info.type(), state_info.bailout_id(), 2842 instruction_zone(), state_info.type(), state_info.bailout_id(),
2941 state_info.state_combine(), parameters, locals, stack, 2843 state_info.state_combine(), parameters, locals, stack,
2942 state_info.shared_info(), outer_state); 2844 state_info.shared_info(), outer_state);
2943 } 2845 }
2944 2846
2945 2847
2946 } // namespace compiler 2848 } // namespace compiler
2947 } // namespace internal 2849 } // namespace internal
2948 } // namespace v8 2850 } // namespace v8
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