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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
| 6 | 6 |
| 7 #if V8_TARGET_ARCH_MIPS | 7 #if V8_TARGET_ARCH_MIPS |
| 8 | 8 |
| 9 #include "src/base/bits.h" | 9 #include "src/base/bits.h" |
| 10 #include "src/base/division-by-constant.h" | 10 #include "src/base/division-by-constant.h" |
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| 557 addu(rd, rs, at); | 557 addu(rd, rs, at); |
| 558 } | 558 } |
| 559 } | 559 } |
| 560 } | 560 } |
| 561 | 561 |
| 562 | 562 |
| 563 void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) { | 563 void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) { |
| 564 if (rt.is_reg()) { | 564 if (rt.is_reg()) { |
| 565 subu(rd, rs, rt.rm()); | 565 subu(rd, rs, rt.rm()); |
| 566 } else { | 566 } else { |
| 567 if (is_int16(rt.imm32_) && !MustUseReg(rt.rmode_)) { | 567 if (is_int16(-rt.imm32_) && !MustUseReg(rt.rmode_)) { |
| 568 addiu(rd, rs, -rt.imm32_); // No subiu instr, use addiu(x, y, -imm). | 568 addiu(rd, rs, -rt.imm32_); // No subiu instr, use addiu(x, y, -imm). |
| 569 } else if (!(-rt.imm32_ & kHiMask) && !MustUseReg(rt.rmode_)) { // Use load |
| 570 // -imm and addu for cases where loading -imm generates one instruction. |
| 571 DCHECK(!rs.is(at)); |
| 572 li(at, -rt.imm32_); |
| 573 addu(rd, rs, at); |
| 569 } else { | 574 } else { |
| 570 // li handles the relocation. | 575 // li handles the relocation. |
| 571 DCHECK(!rs.is(at)); | 576 DCHECK(!rs.is(at)); |
| 572 li(at, rt); | 577 li(at, rt); |
| 573 subu(rd, rs, at); | 578 subu(rd, rs, at); |
| 574 } | 579 } |
| 575 } | 580 } |
| 576 } | 581 } |
| 577 | 582 |
| 578 | 583 |
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| 6630 if (mag.shift > 0) sra(result, result, mag.shift); | 6635 if (mag.shift > 0) sra(result, result, mag.shift); |
| 6631 srl(at, dividend, 31); | 6636 srl(at, dividend, 31); |
| 6632 Addu(result, result, Operand(at)); | 6637 Addu(result, result, Operand(at)); |
| 6633 } | 6638 } |
| 6634 | 6639 |
| 6635 | 6640 |
| 6636 } // namespace internal | 6641 } // namespace internal |
| 6637 } // namespace v8 | 6642 } // namespace v8 |
| 6638 | 6643 |
| 6639 #endif // V8_TARGET_ARCH_MIPS | 6644 #endif // V8_TARGET_ARCH_MIPS |
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