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Side by Side Diff: src/assembler.h

Issue 284153004: Avoid flushing the icache unnecessarily when updating target addresses in code. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Update SKIP_ICACHE_FLUSH_IF_ATOMIC to only skip when patching a single instruction. Created 6 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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269 #if V8_TARGET_ARCH_ARM64 269 #if V8_TARGET_ARCH_ARM64
270 // On ARM64, the Assembler keeps track of pointers to Labels to resolve 270 // On ARM64, the Assembler keeps track of pointers to Labels to resolve
271 // branches to distant targets. Copying labels would confuse the Assembler. 271 // branches to distant targets. Copying labels would confuse the Assembler.
272 DISALLOW_COPY_AND_ASSIGN(Label); // NOLINT 272 DISALLOW_COPY_AND_ASSIGN(Label); // NOLINT
273 #endif 273 #endif
274 }; 274 };
275 275
276 276
277 enum SaveFPRegsMode { kDontSaveFPRegs, kSaveFPRegs }; 277 enum SaveFPRegsMode { kDontSaveFPRegs, kSaveFPRegs };
278 278
279 // Specifies whether to perform icache flush operations on RelocInfo updates.
280 // If FLUSH_ICACHE_IF_NEEDED, the icache will always be flushed if an
281 // instruction was modifed. If SKIP_ICACHE_FLUSH_IF_ATOMIC, the icache flush
282 // will be skipped if the update can be made atomically such that the CPU will
283 // execute either the complete old instruction sequence, or the complete new
284 // sequence. If SKIP_ICACHE_FLUSH the flush will always be skipped.
285 enum ICacheFlushMode { FLUSH_ICACHE_IF_NEEDED,
286 SKIP_ICACHE_FLUSH_IF_ATOMIC,
287 SKIP_ICACHE_FLUSH };
279 288
280 // ----------------------------------------------------------------------------- 289 // -----------------------------------------------------------------------------
281 // Relocation information 290 // Relocation information
282 291
283 292
284 // Relocation information consists of the address (pc) of the datum 293 // Relocation information consists of the address (pc) of the datum
285 // to which the relocation information applies, the relocation mode 294 // to which the relocation information applies, the relocation mode
286 // (rmode), and an optional data field. The relocation mode may be 295 // (rmode), and an optional data field. The relocation mode may be
287 // "descriptive" and not indicate a need for relocation, but simply 296 // "descriptive" and not indicate a need for relocation, but simply
288 // describe a property of the datum. Such rmodes are useful for GC 297 // describe a property of the datum. Such rmodes are useful for GC
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353 LAST_REAL_RELOC_MODE = VENEER_POOL, 362 LAST_REAL_RELOC_MODE = VENEER_POOL,
354 FIRST_PSEUDO_RELOC_MODE = CODE_AGE_SEQUENCE, 363 FIRST_PSEUDO_RELOC_MODE = CODE_AGE_SEQUENCE,
355 LAST_PSEUDO_RELOC_MODE = CODE_AGE_SEQUENCE, 364 LAST_PSEUDO_RELOC_MODE = CODE_AGE_SEQUENCE,
356 LAST_CODE_ENUM = DEBUG_BREAK, 365 LAST_CODE_ENUM = DEBUG_BREAK,
357 LAST_GCED_ENUM = CELL, 366 LAST_GCED_ENUM = CELL,
358 // Modes <= LAST_COMPACT_ENUM are guaranteed to have compact encoding. 367 // Modes <= LAST_COMPACT_ENUM are guaranteed to have compact encoding.
359 LAST_COMPACT_ENUM = CODE_TARGET_WITH_ID, 368 LAST_COMPACT_ENUM = CODE_TARGET_WITH_ID,
360 LAST_STANDARD_NONCOMPACT_ENUM = INTERNAL_REFERENCE 369 LAST_STANDARD_NONCOMPACT_ENUM = INTERNAL_REFERENCE
361 }; 370 };
362 371
363
364 RelocInfo() {} 372 RelocInfo() {}
365 373
366 RelocInfo(byte* pc, Mode rmode, intptr_t data, Code* host) 374 RelocInfo(byte* pc, Mode rmode, intptr_t data, Code* host)
367 : pc_(pc), rmode_(rmode), data_(data), host_(host) { 375 : pc_(pc), rmode_(rmode), data_(data), host_(host) {
368 } 376 }
369 RelocInfo(byte* pc, double data64) 377 RelocInfo(byte* pc, double data64)
370 : pc_(pc), rmode_(NONE64), data64_(data64), host_(NULL) { 378 : pc_(pc), rmode_(NONE64), data64_(data64), host_(NULL) {
371 } 379 }
372 380
373 static inline bool IsRealRelocMode(Mode mode) { 381 static inline bool IsRealRelocMode(Mode mode) {
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461 469
462 // If true, the pointer this relocation info refers to is an entry in the 470 // If true, the pointer this relocation info refers to is an entry in the
463 // constant pool, otherwise the pointer is embedded in the instruction stream. 471 // constant pool, otherwise the pointer is embedded in the instruction stream.
464 bool IsInConstantPool(); 472 bool IsInConstantPool();
465 473
466 // Read/modify the code target in the branch/call instruction 474 // Read/modify the code target in the branch/call instruction
467 // this relocation applies to; 475 // this relocation applies to;
468 // can only be called if IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_) 476 // can only be called if IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
469 INLINE(Address target_address()); 477 INLINE(Address target_address());
470 INLINE(void set_target_address(Address target, 478 INLINE(void set_target_address(Address target,
471 WriteBarrierMode mode = UPDATE_WRITE_BARRIER)); 479 WriteBarrierMode write_barrier_mode =
480 UPDATE_WRITE_BARRIER,
481 ICacheFlushMode icache_flush_mode =
482 FLUSH_ICACHE_IF_NEEDED));
472 INLINE(Object* target_object()); 483 INLINE(Object* target_object());
473 INLINE(Handle<Object> target_object_handle(Assembler* origin)); 484 INLINE(Handle<Object> target_object_handle(Assembler* origin));
474 INLINE(void set_target_object(Object* target, 485 INLINE(void set_target_object(Object* target,
475 WriteBarrierMode mode = UPDATE_WRITE_BARRIER)); 486 WriteBarrierMode write_barrier_mode =
487 UPDATE_WRITE_BARRIER,
488 ICacheFlushMode icache_flush_mode =
489 FLUSH_ICACHE_IF_NEEDED));
476 INLINE(Address target_runtime_entry(Assembler* origin)); 490 INLINE(Address target_runtime_entry(Assembler* origin));
477 INLINE(void set_target_runtime_entry(Address target, 491 INLINE(void set_target_runtime_entry(Address target,
478 WriteBarrierMode mode = 492 WriteBarrierMode write_barrier_mode =
479 UPDATE_WRITE_BARRIER)); 493 UPDATE_WRITE_BARRIER,
494 ICacheFlushMode icache_flush_mode =
495 FLUSH_ICACHE_IF_NEEDED));
480 INLINE(Cell* target_cell()); 496 INLINE(Cell* target_cell());
481 INLINE(Handle<Cell> target_cell_handle()); 497 INLINE(Handle<Cell> target_cell_handle());
482 INLINE(void set_target_cell(Cell* cell, 498 INLINE(void set_target_cell(Cell* cell,
483 WriteBarrierMode mode = UPDATE_WRITE_BARRIER)); 499 WriteBarrierMode write_barrier_mode =
500 UPDATE_WRITE_BARRIER,
501 ICacheFlushMode icache_flush_mode =
502 FLUSH_ICACHE_IF_NEEDED));
484 INLINE(Handle<Object> code_age_stub_handle(Assembler* origin)); 503 INLINE(Handle<Object> code_age_stub_handle(Assembler* origin));
485 INLINE(Code* code_age_stub()); 504 INLINE(Code* code_age_stub());
486 INLINE(void set_code_age_stub(Code* stub)); 505 INLINE(void set_code_age_stub(Code* stub));
487 506
488 // Returns the address of the constant pool entry where the target address 507 // Returns the address of the constant pool entry where the target address
489 // is held. This should only be called if IsInConstantPool returns true. 508 // is held. This should only be called if IsInConstantPool returns true.
490 INLINE(Address constant_pool_entry_address()); 509 INLINE(Address constant_pool_entry_address());
491 510
492 // Read the address of the word containing the target_address in an 511 // Read the address of the word containing the target_address in an
493 // instruction stream. What this means exactly is architecture-independent. 512 // instruction stream. What this means exactly is architecture-independent.
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1129 1148
1130 private: 1149 private:
1131 int32_t multiplier_; 1150 int32_t multiplier_;
1132 int32_t shift_; 1151 int32_t shift_;
1133 }; 1152 };
1134 1153
1135 1154
1136 } } // namespace v8::internal 1155 } } // namespace v8::internal
1137 1156
1138 #endif // V8_ASSEMBLER_H_ 1157 #endif // V8_ASSEMBLER_H_
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