Adds far-branches to arm64.

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 // An extra check since we are assuming the existence of /proc/cpuinfo below.
 #if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID)
 #error ARM64 cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
+DEFINE_FLAG(bool, use_far_branches, false, "Always use far branches");
 DEFINE_FLAG(bool, print_stop_message, false, "Print stop message.");
 DECLARE_FLAG(bool, inline_alloc);
 
 
 Assembler::Assembler(bool use_far_branches)
     : buffer_(),
       object_pool_(GrowableObjectArray::Handle()),
       patchable_pool_entries_(),
       prologue_offset_(-1),
       use_far_branches_(use_far_branches),
@@ skipping 83 matching lines @@
   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 
-// TODO(zra): Support for far branches. Requires loading large immediates.
 void Assembler::Bind(Label* label) {
   ASSERT(!label->IsBound());
-  intptr_t bound_pc = buffer_.Size();
+  const intptr_t bound_pc = buffer_.Size();
 
   while (label->IsLinked()) {
     const int64_t position = label->Position();
     const int64_t dest = bound_pc - position;
-    const int32_t next = buffer_.Load<int32_t>(position);
-    const int32_t encoded = EncodeImm19BranchOffset(dest, next);
-    buffer_.Store<int32_t>(position, encoded);
-    label->position_ = DecodeImm19BranchOffset(next);
+    if (use_far_branches() /*&& !CanEncodeImm19BranchOffset(dest)*/) {
+      // Far branches are enabled, and we can't encode the branch offset in
+      // 19 bits.
+
+      // Grab the guard branch instruction.
+      const int32_t guard_branch =
+          buffer_.Load<int32_t>(position + 0 * Instr::kInstrSize);
+
+      // Grab the far branch instruction.
+      const int32_t far_branch =
+          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
+
+      const Condition c = DecodeImm19BranchCondition(guard_branch);
+
+      // Grab the link to the next branch.
+      const int32_t next = DecodeImm26BranchOffset(far_branch);
+
+      // offset is from the branch instruction.
+      const int64_t offset = dest - Instr::kInstrSize;
+
+      // Encode the branch.
+      const int32_t encoded_branch =
+          EncodeImm26BranchOffset(offset, far_branch);
+
+      // Replace NV conditioned branches with nops.
+      if (c == NV) {
+        buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize,
+                               Instr::kNopInstruction);
+      }
+
+      // Write the far branch into the buffer, and link to the next branch.
+      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, encoded_branch);
+      label->position_ = next;
+    } else if (use_far_branches() && CanEncodeImm19BranchOffset(dest)) {
+      // We assembled a far branch, but we don't need it. Replace with a near
+      // branch.
+
+      // Grab the guarding branch instruction.
+      const int32_t guard_branch =
+          buffer_.Load<int32_t>(position + 0 * Instr::kInstrSize);
+
+      // Grab the far branch instruction.
+      const int32_t far_branch =
+          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
+
+      // Grab the link to the next branch.
+      const int32_t next = DecodeImm26BranchOffset(far_branch);
+
+      // Re-target the near branch and flip the conditional sense.
+      int32_t encoded_guard_branch =
+          EncodeImm19BranchOffset(dest, guard_branch);
+      Condition c = DecodeImm19BranchCondition(encoded_guard_branch);
+      encoded_guard_branch = EncodeImm19BranchCondition(
+          InvertCondition(c), encoded_guard_branch);
+
+      // Write back re-encoded instructions. Far branch becomes nop.
+      buffer_.Store<int32_t>(
+          position + 0 * Instr::kInstrSize, encoded_guard_branch);
+      buffer_.Store<int32_t>(
+          position + 1 * Instr::kInstrSize, Instr::kNopInstruction);
+      label->position_ = next;
+    } else {
+      const int32_t next = buffer_.Load<int32_t>(position);
+      const int32_t encoded = EncodeImm19BranchOffset(dest, next);
+      buffer_.Store<int32_t>(position, encoded);
+      label->position_ = DecodeImm19BranchOffset(next);
+    }
   }
   label->BindTo(bound_pc);
 }
 
 
 void Assembler::Stop(const char* message) {
   if (FLAG_print_stop_message) {
     UNIMPLEMENTED();
   }
   Label stop;
@@ skipping 790 matching lines @@
     Register object, intptr_t class_id, Register pp) {
   LoadClassId(TMP, object, pp);
   CompareImmediate(TMP, class_id, pp);
 }
 
 
 // Frame entry and exit.
 void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
   // Reserve space for arguments and align frame before entering
   // the C++ world.
-  AddImmediate(SP, SP, -frame_space, kNoPP);
+  if (frame_space != 0) {
+    AddImmediate(SP, SP, -frame_space, kNoPP);
+  }
   if (OS::ActivationFrameAlignment() > 1) {
     mov(TMP, SP);  // SP can't be register operand of andi.
     andi(TMP, TMP, ~(OS::ActivationFrameAlignment() - 1));
     mov(SP, TMP);
   }
 }
 
 
 void Assembler::EnterFrame(intptr_t frame_size) {
   Push(LR);
@@ skipping 291 matching lines @@
     LoadImmediate(TMP, tags, pp);
     StoreFieldToOffset(TMP, instance_reg, Object::tags_offset(), pp);
   } else {
     b(failure);
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64