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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
| (...skipping 174 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 185 V(Mips64I32x4Ne) \ | 185 V(Mips64I32x4Ne) \ |
| 186 V(Mips64I32x4Shl) \ | 186 V(Mips64I32x4Shl) \ |
| 187 V(Mips64I32x4ShrS) \ | 187 V(Mips64I32x4ShrS) \ |
| 188 V(Mips64I32x4ShrU) \ | 188 V(Mips64I32x4ShrU) \ |
| 189 V(Mips64I32x4MaxU) \ | 189 V(Mips64I32x4MaxU) \ |
| 190 V(Mips64I32x4MinU) \ | 190 V(Mips64I32x4MinU) \ |
| 191 V(Mips64S32x4Select) \ | 191 V(Mips64S32x4Select) \ |
| 192 V(Mips64F32x4Abs) \ | 192 V(Mips64F32x4Abs) \ |
| 193 V(Mips64F32x4Neg) \ | 193 V(Mips64F32x4Neg) \ |
| 194 V(Mips64F32x4RecipApprox) \ | 194 V(Mips64F32x4RecipApprox) \ |
| 195 V(Mips64F32x4RecipRefine) \ | |
| 196 V(Mips64F32x4RecipSqrtApprox) \ | 195 V(Mips64F32x4RecipSqrtApprox) \ |
| 197 V(Mips64F32x4RecipSqrtRefine) \ | |
| 198 V(Mips64F32x4Add) \ | 196 V(Mips64F32x4Add) \ |
| 199 V(Mips64F32x4Sub) \ | 197 V(Mips64F32x4Sub) \ |
| 200 V(Mips64F32x4Mul) \ | 198 V(Mips64F32x4Mul) \ |
| 201 V(Mips64F32x4Max) \ | 199 V(Mips64F32x4Max) \ |
| 202 V(Mips64F32x4Min) \ | 200 V(Mips64F32x4Min) \ |
| 203 V(Mips64F32x4Eq) \ | 201 V(Mips64F32x4Eq) \ |
| 204 V(Mips64F32x4Ne) \ | 202 V(Mips64F32x4Ne) \ |
| 205 V(Mips64F32x4Lt) \ | 203 V(Mips64F32x4Lt) \ |
| 206 V(Mips64F32x4Le) \ | 204 V(Mips64F32x4Le) \ |
| 207 V(Mips64I32x4SConvertF32x4) \ | 205 V(Mips64I32x4SConvertF32x4) \ |
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| 224 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 222 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 225 V(MRI) /* [%r0 + K] */ \ | 223 V(MRI) /* [%r0 + K] */ \ |
| 226 V(MRR) /* [%r0 + %r1] */ | 224 V(MRR) /* [%r0 + %r1] */ |
| 227 | 225 |
| 228 | 226 |
| 229 } // namespace compiler | 227 } // namespace compiler |
| 230 } // namespace internal | 228 } // namespace internal |
| 231 } // namespace v8 | 229 } // namespace v8 |
| 232 | 230 |
| 233 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 231 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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