Fix an undetected Smi overflow on ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2210 matching lines @@
   // to by this code sequence.
   // For added code robustness, use 'blx lr' in a patchable sequence and
   // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
   const int32_t offset =
       Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag;
   LoadWordFromPoolOffset(LR, offset);
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
-void Assembler::BranchLinkStore(const ExternalLabel* label, Address ad) {
-  // TODO(regis): Revisit this code sequence.
-  LoadImmediate(IP, label->address());  // Target address is never patched.
-  str(PC, ad);
-  blx(IP);  // Use blx instruction so that the return branch prediction works.
-}
-
-
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
   LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::LoadPatchableImmediate(
     Register rd, int32_t value, Condition cond) {
@@ skipping 49 matching lines @@
     LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
     vmovsr(sd, IP, cond);
   }
 }
 
 
 void Assembler::LoadDImmediate(DRegister dd,
                                double value,
                                Register scratch,
                                Condition cond) {
-  // TODO(regis): Revisit this code sequence.
   ASSERT(scratch != PC);
   ASSERT(scratch != IP);
   if (!vmovd(dd, value, cond)) {
     // A scratch register and IP are needed to load an arbitrary double.
     ASSERT(scratch != kNoRegister);
     int64_t imm64 = bit_cast<int64_t, double>(value);
     LoadImmediate(IP, Utils::Low32Bits(imm64), cond);
     LoadImmediate(scratch, Utils::High32Bits(imm64), cond);
     vmovdrr(dd, IP, scratch, cond);
   }
@@ skipping 182 matching lines @@
       add(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
+    // Handles value == kMinInt32.
     adds(rd, rn, shifter_op, cond);
   } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
+    ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
     subs(rd, rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     if (ShifterOperand::CanHold(~value, &shifter_op)) {
       mvn(IP, shifter_op, cond);
       adds(rd, rn, ShifterOperand(IP), cond);
     } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
+      ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, shifter_op, cond);
       subs(rd, rn, ShifterOperand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
       adds(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
-void Assembler::AddImmediateWithCarry(Register rd, Register rn, int32_t value,
-                                     Condition cond) {
+void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
+                                    Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
-    adc(rd, rn, shifter_op, cond);
-  } else if (ShifterOperand::CanHold(-value - 1, &shifter_op)) {
-    sbc(rd, rn, shifter_op, cond);
+    // Handles value == kMinInt32.
+    subs(rd, rn, shifter_op, cond);
+  } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
+    ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
+    adds(rd, rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     if (ShifterOperand::CanHold(~value, &shifter_op)) {
       mvn(IP, shifter_op, cond);
-      adc(rd, rn, ShifterOperand(IP), cond);
-    } else if (ShifterOperand::CanHold(~(-value - 1), &shifter_op)) {
+      subs(rd, rn, ShifterOperand(IP), cond);
+    } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
+      ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
       mvn(IP, shifter_op, cond);
-      sbc(rd, rn, ShifterOperand(IP), cond);
+      adds(rd, rn, ShifterOperand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
-      adc(rd, rn, ShifterOperand(IP), cond);
+      subs(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
                              Condition cond) {
   ShifterOperand op;
   if (ShifterOperand::CanHold(imm, &op)) {
     and_(rd, rs, ShifterOperand(op), cond);
@@ skipping 470 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM