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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
7 | 7 |
8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
9 #include "vm/cpu.h" | 9 #include "vm/cpu.h" |
10 #include "vm/longjump.h" | 10 #include "vm/longjump.h" |
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2221 // to by this code sequence. | 2221 // to by this code sequence. |
2222 // For added code robustness, use 'blx lr' in a patchable sequence and | 2222 // For added code robustness, use 'blx lr' in a patchable sequence and |
2223 // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors). | 2223 // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors). |
2224 const int32_t offset = | 2224 const int32_t offset = |
2225 Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag; | 2225 Array::data_offset() + 4*AddExternalLabel(label) - kHeapObjectTag; |
2226 LoadWordFromPoolOffset(LR, offset); | 2226 LoadWordFromPoolOffset(LR, offset); |
2227 blx(LR); // Use blx instruction so that the return branch prediction works. | 2227 blx(LR); // Use blx instruction so that the return branch prediction works. |
2228 } | 2228 } |
2229 | 2229 |
2230 | 2230 |
2231 void Assembler::BranchLinkStore(const ExternalLabel* label, Address ad) { | |
2232 // TODO(regis): Revisit this code sequence. | |
2233 LoadImmediate(IP, label->address()); // Target address is never patched. | |
2234 str(PC, ad); | |
2235 blx(IP); // Use blx instruction so that the return branch prediction works. | |
2236 } | |
2237 | |
2238 | |
2239 void Assembler::BranchLinkOffset(Register base, int32_t offset) { | 2231 void Assembler::BranchLinkOffset(Register base, int32_t offset) { |
2240 ASSERT(base != PC); | 2232 ASSERT(base != PC); |
2241 ASSERT(base != IP); | 2233 ASSERT(base != IP); |
2242 LoadFromOffset(kWord, IP, base, offset); | 2234 LoadFromOffset(kWord, IP, base, offset); |
2243 blx(IP); // Use blx instruction so that the return branch prediction works. | 2235 blx(IP); // Use blx instruction so that the return branch prediction works. |
2244 } | 2236 } |
2245 | 2237 |
2246 | 2238 |
2247 void Assembler::LoadPatchableImmediate( | 2239 void Assembler::LoadPatchableImmediate( |
2248 Register rd, int32_t value, Condition cond) { | 2240 Register rd, int32_t value, Condition cond) { |
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2298 LoadImmediate(IP, bit_cast<int32_t, float>(value), cond); | 2290 LoadImmediate(IP, bit_cast<int32_t, float>(value), cond); |
2299 vmovsr(sd, IP, cond); | 2291 vmovsr(sd, IP, cond); |
2300 } | 2292 } |
2301 } | 2293 } |
2302 | 2294 |
2303 | 2295 |
2304 void Assembler::LoadDImmediate(DRegister dd, | 2296 void Assembler::LoadDImmediate(DRegister dd, |
2305 double value, | 2297 double value, |
2306 Register scratch, | 2298 Register scratch, |
2307 Condition cond) { | 2299 Condition cond) { |
2308 // TODO(regis): Revisit this code sequence. | |
2309 ASSERT(scratch != PC); | 2300 ASSERT(scratch != PC); |
2310 ASSERT(scratch != IP); | 2301 ASSERT(scratch != IP); |
2311 if (!vmovd(dd, value, cond)) { | 2302 if (!vmovd(dd, value, cond)) { |
2312 // A scratch register and IP are needed to load an arbitrary double. | 2303 // A scratch register and IP are needed to load an arbitrary double. |
2313 ASSERT(scratch != kNoRegister); | 2304 ASSERT(scratch != kNoRegister); |
2314 int64_t imm64 = bit_cast<int64_t, double>(value); | 2305 int64_t imm64 = bit_cast<int64_t, double>(value); |
2315 LoadImmediate(IP, Utils::Low32Bits(imm64), cond); | 2306 LoadImmediate(IP, Utils::Low32Bits(imm64), cond); |
2316 LoadImmediate(scratch, Utils::High32Bits(imm64), cond); | 2307 LoadImmediate(scratch, Utils::High32Bits(imm64), cond); |
2317 vmovdrr(dd, IP, scratch, cond); | 2308 vmovdrr(dd, IP, scratch, cond); |
2318 } | 2309 } |
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2501 add(rd, rn, ShifterOperand(IP), cond); | 2492 add(rd, rn, ShifterOperand(IP), cond); |
2502 } | 2493 } |
2503 } | 2494 } |
2504 } | 2495 } |
2505 | 2496 |
2506 | 2497 |
2507 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value, | 2498 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value, |
2508 Condition cond) { | 2499 Condition cond) { |
2509 ShifterOperand shifter_op; | 2500 ShifterOperand shifter_op; |
2510 if (ShifterOperand::CanHold(value, &shifter_op)) { | 2501 if (ShifterOperand::CanHold(value, &shifter_op)) { |
| 2502 // Handles value == kMinInt32. |
2511 adds(rd, rn, shifter_op, cond); | 2503 adds(rd, rn, shifter_op, cond); |
2512 } else if (ShifterOperand::CanHold(-value, &shifter_op)) { | 2504 } else if (ShifterOperand::CanHold(-value, &shifter_op)) { |
| 2505 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection. |
2513 subs(rd, rn, shifter_op, cond); | 2506 subs(rd, rn, shifter_op, cond); |
2514 } else { | 2507 } else { |
2515 ASSERT(rn != IP); | 2508 ASSERT(rn != IP); |
2516 if (ShifterOperand::CanHold(~value, &shifter_op)) { | 2509 if (ShifterOperand::CanHold(~value, &shifter_op)) { |
2517 mvn(IP, shifter_op, cond); | 2510 mvn(IP, shifter_op, cond); |
2518 adds(rd, rn, ShifterOperand(IP), cond); | 2511 adds(rd, rn, ShifterOperand(IP), cond); |
2519 } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { | 2512 } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { |
| 2513 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection. |
2520 mvn(IP, shifter_op, cond); | 2514 mvn(IP, shifter_op, cond); |
2521 subs(rd, rn, ShifterOperand(IP), cond); | 2515 subs(rd, rn, ShifterOperand(IP), cond); |
2522 } else { | 2516 } else { |
2523 LoadDecodableImmediate(IP, value, cond); | 2517 LoadDecodableImmediate(IP, value, cond); |
2524 adds(rd, rn, ShifterOperand(IP), cond); | 2518 adds(rd, rn, ShifterOperand(IP), cond); |
2525 } | 2519 } |
2526 } | 2520 } |
2527 } | 2521 } |
2528 | 2522 |
2529 | 2523 |
2530 void Assembler::AddImmediateWithCarry(Register rd, Register rn, int32_t value, | 2524 void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value, |
2531 Condition cond) { | 2525 Condition cond) { |
2532 ShifterOperand shifter_op; | 2526 ShifterOperand shifter_op; |
2533 if (ShifterOperand::CanHold(value, &shifter_op)) { | 2527 if (ShifterOperand::CanHold(value, &shifter_op)) { |
2534 adc(rd, rn, shifter_op, cond); | 2528 // Handles value == kMinInt32. |
2535 } else if (ShifterOperand::CanHold(-value - 1, &shifter_op)) { | 2529 subs(rd, rn, shifter_op, cond); |
2536 sbc(rd, rn, shifter_op, cond); | 2530 } else if (ShifterOperand::CanHold(-value, &shifter_op)) { |
| 2531 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection. |
| 2532 adds(rd, rn, shifter_op, cond); |
2537 } else { | 2533 } else { |
2538 ASSERT(rn != IP); | 2534 ASSERT(rn != IP); |
2539 if (ShifterOperand::CanHold(~value, &shifter_op)) { | 2535 if (ShifterOperand::CanHold(~value, &shifter_op)) { |
2540 mvn(IP, shifter_op, cond); | 2536 mvn(IP, shifter_op, cond); |
2541 adc(rd, rn, ShifterOperand(IP), cond); | 2537 subs(rd, rn, ShifterOperand(IP), cond); |
2542 } else if (ShifterOperand::CanHold(~(-value - 1), &shifter_op)) { | 2538 } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { |
| 2539 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection. |
2543 mvn(IP, shifter_op, cond); | 2540 mvn(IP, shifter_op, cond); |
2544 sbc(rd, rn, ShifterOperand(IP), cond); | 2541 adds(rd, rn, ShifterOperand(IP), cond); |
2545 } else { | 2542 } else { |
2546 LoadDecodableImmediate(IP, value, cond); | 2543 LoadDecodableImmediate(IP, value, cond); |
2547 adc(rd, rn, ShifterOperand(IP), cond); | 2544 subs(rd, rn, ShifterOperand(IP), cond); |
2548 } | 2545 } |
2549 } | 2546 } |
2550 } | 2547 } |
2551 | 2548 |
2552 | 2549 |
2553 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm, | 2550 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm, |
2554 Condition cond) { | 2551 Condition cond) { |
2555 ShifterOperand op; | 2552 ShifterOperand op; |
2556 if (ShifterOperand::CanHold(imm, &op)) { | 2553 if (ShifterOperand::CanHold(imm, &op)) { |
2557 and_(rd, rs, ShifterOperand(op), cond); | 2554 and_(rd, rs, ShifterOperand(op), cond); |
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3028 | 3025 |
3029 | 3026 |
3030 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3027 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3031 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3028 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3032 return fpu_reg_names[reg]; | 3029 return fpu_reg_names[reg]; |
3033 } | 3030 } |
3034 | 3031 |
3035 } // namespace dart | 3032 } // namespace dart |
3036 | 3033 |
3037 #endif // defined TARGET_ARCH_ARM | 3034 #endif // defined TARGET_ARCH_ARM |
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