Index: src/compiler/mips/code-generator-mips.cc |
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc |
index 476099e5cfedce23c01792ccef2832ab450ffb80..18a8c293e4f1cca4b0a383c68eceea92e4212ab3 100644 |
--- a/src/compiler/mips/code-generator-mips.cc |
+++ b/src/compiler/mips/code-generator-mips.cc |
@@ -775,8 +775,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( |
case kArchStackSlot: { |
FrameOffset offset = |
frame_access_state()->GetFrameOffset(i.InputInt32(0)); |
- __ Addu(i.OutputRegister(), offset.from_stack_pointer() ? sp : fp, |
- Operand(offset.offset())); |
+ Register base_reg = offset.from_stack_pointer() ? sp : fp; |
+ __ Addu(i.OutputRegister(), base_reg, Operand(offset.offset())); |
+ int alignment = i.InputInt32(1); |
+ DCHECK(alignment == 0 || alignment == 4 || alignment == 8 || |
+ alignment == 16); |
+ if (FLAG_debug_code && alignment > 0) { |
+ // Verify that the output_register is properly aligned |
+ __ And(kScratchReg, i.OutputRegister(), Operand(kPointerSize - 1)); |
+ __ Assert(eq, kAllocationIsNotDoubleAligned, kScratchReg, |
+ Operand(zero_reg)); |
+ } |
+ |
+ if (alignment == 2 * kPointerSize) { |
+ Label done; |
+ __ Addu(kScratchReg, base_reg, Operand(offset.offset())); |
+ __ And(kScratchReg, kScratchReg, Operand(alignment - 1)); |
+ __ BranchShort(&done, eq, kScratchReg, Operand(zero_reg)); |
+ __ Addu(i.OutputRegister(), i.OutputRegister(), kPointerSize); |
+ __ bind(&done); |
+ } else if (alignment > 2 * kPointerSize) { |
+ Label done; |
+ __ Addu(kScratchReg, base_reg, Operand(offset.offset())); |
+ __ And(kScratchReg, kScratchReg, Operand(alignment - 1)); |
+ __ BranchShort(&done, eq, kScratchReg, Operand(zero_reg)); |
+ __ li(kScratchReg2, alignment); |
+ __ Subu(kScratchReg2, kScratchReg2, Operand(kScratchReg)); |
+ __ Addu(i.OutputRegister(), i.OutputRegister(), kScratchReg2); |
+ __ bind(&done); |
+ } |
break; |
} |
case kIeee754Float64Acos: |